How to get Timer to initiate a DMA request from SPI or any peripheral

[mandrake]

Posted on December 21, 2011 at 17:29

(I moved my question to here from STM32F4-DISCOVERY. Thought this would be the proper place to ask for help).

I am using TIM2_CH3 configured for a DMA1 request on Stream1_Channel3. On Output Compare I would like TIM2_CH3 to trigger SPI1 to begin a DMA2 request on Stream5_Channel3. How do I associate the TIM2_CH3 event with SPI1 DMA2 using Stream5_Channel3 (for example)? Do I just trigger a DMA1 to transfer memory to SPI1->DR? I don't understand the usage of TIM-DMABase in TIM_DCR register. Is this only to perform a DMA transfer between a TIM register and memory?

[Tesla DeLorean]

Posted on December 21, 2011 at 18:22

The DMA peripheral register can point to anything you want. Be it the CCR register to load the PWM from a table, or the DAC output register, or some other timer completely. The DMA is then paced at the update (or whatever trigger source you selected) of the timer it is wired too.

The reference manual (DM00031020 RM0090) spells out the DMA request sources. DMA1 Stream5 Channel3 has to come from TIM2_CH1

[mandrake]

Posted on December 22, 2011 at 11:37

I am getting confused between the peripheral making the DMA request and the target peripheral (memory to peripheral transfer).

Do both peripherals have to be on the same DMA/APB bus? Do they have to be or can they be on the same or different stream? Or does the target peripheral have to be the same as the requesting peripheral? You have implied that the target peripheral can be any, on either bus, i.e. anything goes in DMA_SxPAR. I am trying to use TIM2_CH3 to request a DMA1 on Stream1 Channel 3 that initiates another DMA transfer of memory to SPI1_DR on DMA2 Stream 5 Channel 3. The initial request is not being executed. (I can get TIM2 to make a DMA transfer from memory to a TIM2 register.)

[Tesla DeLorean]

Posted on December 22, 2011 at 15:45

You'll have to read through the documentation thoroughly.

Yes, there do look to be constraints on what can talk to what, only one of the units can do memory-to-memory, and neither of them can DMA into the 64KB of SRAM tightly coupled to the processor (CCM aka TCM, or ''Chip RAM''). There are very specific DMA request sources, I haven't checked if the sources cross APB boundaries, I'm not sure it matters, the constraint is the MEM->APBx, and APBx->MEM interaction, ie what bus the read/write request occurs on, not the source of the signal making the request. What you're try to describe is awfully convoluted. Perhaps you can explain what you're trying to achieve at a higher level, with some indication of the timing/bandwidth expected.

[mandrake]

Posted on December 22, 2011 at 16:29

Thanks Clive. Believe me, I have read RM0090 a zillion times.

What I am trying to do is initiate a spi DMA to transmit at timed intervals using a timer. I can get this to work using timer interrupts. I would like this to happen in background using a timer DMA request. I think I am pretty close to finding out what is going on. Hopefully I will do some more tests today with regards to bus constraints and report back.

[Tesla DeLorean]

Posted on December 22, 2011 at 18:18

Ok, but I don't understand why that would that would take 2 DMA channels to achieve.

Assuming SPI1 (APB2 DMA2) TIM1_UP (Periodicity from Prescale and Period) DMA2 Stream5 Channel6 Peripheral Register SPI1->DR Also TIM1_CH1 (Counter Compare), DMA2 Stream1 Channel6 A template of the CCR advance method is shown in \STMicro\STM32F4-Discovery_FW_V1.1.0\Project\Audio_playback_and_record\src\main.c Personally I'd go for the update method, requiring no TIM interrupt, and chain the DMA transfers on the TC interrupt. You'd clearly need to pace the SPI  below it's output rate, as the DMA isn't going to care what the TXE flags is doing, so it doesn't saturate/overrun.

[mandrake]

Posted on December 22, 2011 at 21:20

It appears that both the requesting peripheral and the target peripheral must be on the same bus.