What are you trying to calculate/accomplish ?
It is much faster than the ADC can run.
It is not entirely predictable due to contention and other bus traffic/speeds. For the sake of argument it is several AHB cycles.
Normally the ADC is limiting, and not stalled by the transfer. If you want to pace the ADC at a specific frequency with a TIM, and just let the DMA move the data when it is complete. The DMA HT/TC interrupts occur after the transfer completes.
