How to determine proper DSI, LTDC and HDMI timings?

[JKaz.1]

This is my first time working with any DSI/LTDC/HDMI related stuff, so I'm still figuring a lot of this stuff out and could use some help figuring out how times and clock speeds all interact.

I'm using the STM32H757 Eval board.  I have it working with the on board 800x480 display and purchased one of the HDMI adapters they make for this board.  Using one of the example projects I got that displaying at 720x480 to a standard computer monitor (a 1080p capable BENQ).  I now want to increase the resolution and... can't figure out what I need to change.

The example code sets:

DSI to 40625 Khz
LTDC to 27083 Khz

And it uses these timings

Timing->HSYNC = 62U;
Timing->HBP   = 60U;
Timing->HFP   = 30U;
Timing->VSYNC = 6U;
Timing->VBP   = 19U;
Timing->VFP   = 9U;
Timing->HACT  = 720U;
Timing->VACT  = 480U;

I have no idea how they computed those timings.
I found this website: https://tomverbeure.github.io/video_timings_calculator which has very similar timings, but not exactly the same.  It has numerous columns (that I assume are standards of some kind?), but the closest was CEA-861 with the values

Timing->HSYNC = 62U;
Timing->HBP   = 60U;
Timing->HFP   = 16U;
Timing->VSYNC = 6U;
Timing->VBP   = 30U;
Timing->VFP   = 9U;
Timing->HACT  = 720U;
Timing->VACT  = 480U;

I plugged in those timings and those seem to work.  I don't know why there is a slight discrepancies between the example code and that website, but both seem to work so I guess it's close enough.

Using the same website, I switched to 1280x720 @30Hz and all the frequencies go up and so do the timings.  So I guess I have to change my DSI and LTDC frequencies... but how exactly do those two interact?  Does the DSI just always need to be higher than the LTDC?  Do they have to be at a certain ratio?  The column that was closets to the values in the example code for 720x480 came from the CEA-961 column.  For 720p @30Hz that column has running at more than twice the pixel clock speed of the others (74.25MHz).  The DSI goes up to 62MHz per lane (1Ghz total... which I don't really know how either of those two numbers interact, but I know they're a thing).  62 is less than 74, which is what the LTDC would have to be running at if I used that column.  Is that allowed?  Should I be using a different column?

I know that to do certain resolutions at certain frequencies you need X amount of bandwidth, but I don't really know how those numbers are computed and how that corresponds to requisite clock speeds.

Basically, any direction at all would be greatly appreciated.  With displays things often either work or they don't so it can be difficult to figure out exactly what's wrong  Thanks!

[MM..1]

3 simple conditions :

a / LTDC clock is pixel clock in choiced pixel format 

b / DSI clock is data serial transfer byte clock  x 8 bit clock ... 62.5 x 8 = 500Mbit for one lane

c / MX entering LTDC automatic recalculate DSI porchs

Limits is lane data capacity ... example

1280x 720 x 16 (RGB565) / DSI 1Gbit = max 67,81Hz FPS  (real use 90%)

1280 + porchs x 720 + porchs x 67,81 x0,9  = LTDC clock ...

[JKaz.1]

OK, so LTDC clock rate is not necessarily directly related to the DSI rate and is instead related to the particular formatting being used.
The HDMI module from ST has the ADV7533 chip on it, which says "Automatic input video format timing detection (CEA-861E)", so presumably I want to use the CEA-861 column on that website.
So that means: LTDC must be 74.25 MHz.

If I'm running at RGB888, then my math should be:

1280 x 720 x 24 / 1GBit = 45.21 fps
If I want to run at only 30fps, then I need to configure the DS for 663.5MHz, which means each line needs to be 41.46 MHz in CubeMx.  OK, I think I understand part.  Can the DSI speed be faster than 41.46 MHz, or does it have to match exactly?

I still do not know what to use for the porches though.  The LTDC page of CubeMX has me manually setting the Synchronization Width, Back Porch, and Front Porch for both horizontal and vertical?  ... Do I use the values from that website?

[MM..1]

You still missunderstand. DSI speed is 1Gbit in calculations , you cant underspeed ! If you choice 45FPS then you simply fill max speed and dsi must be 62,5MHz.

Second calculated is LTDC pixel clock no DSI and here for you use my last eq.

Normal DSI displays can use bigger DSI clock as data though from LTDC not lower or equal.

And yes for 30fps you can use lower DSI and right pixel clk. But HDMI DSI bridge is next IC and req meet condition.

[JKaz.1]

Correct, I don't understand.  The example code provided in the STM32H7 framework runs an HDMI display at 720x480.  It has the DSI running at 40.625MHz.

With 1 Gbit of bandwidth, the maximum FPS I can get at 1280x720 is 45.  If I want lower than 45, why can't I lower the DSI?

Edit, Side note:

The STM32H7 framework for the Eval board example that uses the built in monitor uses CubeMX to generate all it's settings, makes it very easy to set up my own CubeMX project.

The example that sets it up for HDMI hard codes everything and does not use CubeMX initialization.  Makes it more difficult to make sure things are configured correctly...

[MM..1]

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@JKaz.1 wrote:

So that means: LTDC must be 74.25 MHz.

....

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You write this and this result to 72Hz fps in normal displays config. This is more as 45 or 30. But yes with big porch numbers you can reduce fps to 30 and use pixel clk 74,25. And yes DSI then use lower speed in video burst modes. But here next condition must meet with 74,25 your memory used for framebuffer require read speed for 24 bit data = 3 x 74,5 result you require 32 bit SDRAM for this etc. read LTDC appnote AN4861 AN4860

[JKaz.1]

Ok, with your help and reading up on AN4861 and 4860, I have a... basic understanding of how this fits together.  I think.  Hopefully.  I still haven't been able to get 1280x720 @ 30 Hz to work... but I think I know why and I don't think it's a thing I can resolve with my current hardware.

I'm using the DSI to HDMI module that ST makes which uses the ADV7533.  The datasheet for that chip says it uses the CEI-861 protocol.  Looking at this website: https://tomverbeure.github.io/video_timings_calculator, the required total Bandwidth for 1280x720 @ 30 is identical to 1280x720 @ 60.  I thought this was a bug in the website, but I found another site (https://trychen.com/feature/video-bandwidth) that says the same thing.  The required bandwidth is 1.7 Gb, which is bigger than the maximum throughput of the H7.  The other protocols required throughput drops in half when you go form 60Hz to 30Hz, so it must be a quirk of this particular protocol.  So, I think that means with this board, I can't run things at this protocol.  Annoying, but I think this all makes sense.

There is still one set of numbers that I can't figure out where they come from.  They're just numbers punched into CubeMX.  I don't know how they're computed or where they come from.  A different St Framework example for a different display had different numbers, so they obviously mean something, but they're the same for the two resolutions provided in the HDMI example, 720x480@60Hz and 720x576@50Hz..

ClockLaneHS2LPTime = 0x14;
ClockLaneLP2HSTime = 0x14;
DataLaneHS2LPTime = 0x0A;
DataLaneLP2HSTime = 0x0A;
DataLaneMaxReadTime = 0x00;
StopWaitTime = 0x00;

[MM..1]

This is nums for transitions times from and to low and high speed modes. DSI display controllers have this in pdf defined as nanosec . Then based on choiced clk for DSI and low speed DSI you calc and enter this times as clock cycles.

And maybe you can test 1280x720 30fps 

[JKaz.1]

I built CubeMX version of the example code, so that instead of hand editing code I can at least use CubeMX to generate code that works for 720x480 and 720x576 but I still can't get 1280x720 working.

If I can't meet the Peak BW of a resolution, would the display not do anything at all or would it flicker and have artifacts (or is that going to be display dependent)?  I'm currently using just a standard 1080p desktop monitor.  I'm actually using the exact same model for my laptop that I'm writing this post on.

1280x720 @ 30Hz has a Peak BW of 1782, but a Line BW of 691 and Active BW of 664.  I obviously can't meet the peak, but I should be able to meet the Line and Active.  I have my DSI set to 700 and it doesn't work. I tried cranking the DSI speed up to 975 and switch from Non Burst Mode with Sync to Burst Mode but that also didn't work.  I do have flickering and minor display artifacts when I do that using the lower resolutions, so I'm probably configuring something wrong with that mode.

This might just be something I can't do using the CEA-861 protocol and the H7 board.  Which is mildly annoying but not a deal breaker as this isn't final harder and HDMI will be handle by an FPGA chip that we are also designing so we have control over the protocol.