2016-12-21 11:37 AM
Hello,
We use LCD interface with SM32F4 , with ILITEK 9341.
According to LCD datasheet is it required that CS will be kept active throught several writings of data/control.
But We see that each write of 8-bit word results in changing the CS from IDLE to active and back to IDLE.
Maybe this can explain our failure to make LCD functional.
SRAM configuration:
LCD interface
chip select NE3.
LCD register select: A0
DATA: 8-bit
What can we do to control CS?
I also see the LCD example with STM32F4 demo, which seems to use SSD2119,
and I see that it also make separate write for command and data, so I wander how it works in EVM.
/**
* @brief Writes to the selected LCD register.
* @param LCD_Reg: address of the selected register.
* @param LCD_RegValue: value to write to the selected register.
* @retval None
*/
void LCD_WriteReg(uint8_t LCD_Reg, uint16_t LCD_RegValue)
{
/* Write 16-bit Index, then Write Reg */
LCD_CMD = LCD_Reg;
/* Write 16-bit Reg */
LCD_Data = LCD_RegValue;
}
Thank you!
Ran
2016-12-21 12:18 PM
According to LCD datasheet is it required that CS will be kept active throught several writings of data/control.
No. In the 8080-style of interface, RD and WR are ANDed (in negative logic) with CS before they are used in the rest of the circuit, so that when both RD and WR are high, CS is ignored.
But you can try - simply don't set the CS (NE3) pin as AF in GPIOx_MODER, rather, set it as GPIO Out. Then, whenever you want to perform accesses the LCD, set that pin low before, and high after the accesses.
JW
2016-12-22 05:49 AM
Hi JW,
Thank you very much for the helpful comments!
Please see image here:
https://drive.google.com/file/d/0B22GsWueReZTVEMtcEk4d0VHeVk/view?usp=sharing
The yellow is CS, and purple WE (write enable)
I think that if both move to high between writings, then it is not good, Right ?
Thanks,
Ran
2016-12-22 06:57 AM
As I've said, it should not matter.