How to calculate ADDSET and DATAST according to SRAM timing graph?

[Ethan1]

I use FSMC in STM32F407 to access external SRAM IS62WV51216. I read RM0090 and AN2784, gives me two fomula

tSU means

here is the timing graph

here is write timing graph

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1. why WE have two falling edges on the left
2. what dose tSU tV mean,where is it in the timing graph please draw it. My ENglish is not good and I have some issues on reading, don`t understand "Data to FSMC_NEx high low to FSMC_A valid setup time + FSMC_NEx".It is conflict.
3. Where is ADDSET and DATAST in STM32 parallal in SRAM timing graph, how to calculate ADDSET and DATAST, I really nead your help.

[Ethan1]

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[Ethan1]

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[Ethan1]

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[Ethan1]

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