I'm working with the STM32F446 microcontroller and I'm using UART with DMA. The size of my UART packets is contained in the 3rd and the 4th packet bytes and I would like to use FIFO on the receive stream to increase the likelihood for successfully reception. While receiving a packet, I get several IDLE interrupts from the UART and DMAx_StreamY->NDTR tells me how much I have received so far. My problem is that with FIFO enabled, the correct amount of bytes that have been transferred to my RAM buffer is 2-3 less than reported by DMAx_StreamY->NDTR. Is there a way to find out when the FIFO has been emptied?
