STM32U5G9 SPI TXP does not clear.

[jeffl.kelley9]

Previously had issues with TXP flag never clearing for interrupt-driven SPI.  Changed some HAL code and got it to work.

Moving on the DMA, the first 8 bytes received match the transmit buffer and the 9th byte matches a byte farther into the transmit buffer.

I suspect that the entire DMA buffer is transmitted at the start filling the transmit FIFO and bytes are dropped until the FIFO gains an empty slot and data can once again enter the FIFO.  

This seems consistent with the TXP flag not properly clearing when the transmit FIFO is full.   

Can anyone tell me what makes the TXP flag not operate?

[TDK]

Show your evidence for showing it's not clearing. Code, or received vs expected data, or something else tangible. It's unlikely the hardware is malfunctioning here, probably the issue lies in code. At high data rates, TXP will never clear as code can't keep up.