First use a SW data fifo implemented with a cyclic buffer.
Then use incoming UART2 RX receive data byte interrupt to feed the FIFO and activate UART1 transmit interrupt when the FIFO is no longer empty.
UART1 is the other end of the SW Fifo and UART1 is disabled when the FIFO gets full (size too small), and transmit data interrupt.
The size of the SW fifo depends on the worst case situation, lags, baudrate differential, if any.
The same mecanism was implemented in portable DVD players with a continuous audio stream unless the player receive a shock : the 2 seconds SW Fifo compensates it and avoid glitchy audio.
