Hi, I am new to the STM32. The function SystemCoreClockUpdate() in the library file system_stm32f10x.c extracts the PLL multipl. factor PLLMUL[3:0] from the RCC_CFGR register. Question: why the '+2' here: pllmull = ( pllmull >> 18) + 2;

[Kmax18]

void SystemCoreClockUpdate (void)

{

  uint32_t tmp = 0, pllmull = 0, pllsource = 0;

  /* Get SYSCLK source -------------------------------------------------------*/

  tmp = RCC->CFGR & RCC_CFGR_SWS;

  switch (tmp)

  {

    case 0x00:  /* HSI used as system clock */

      SystemCoreClock = HSI_VALUE;

      break;

    case 0x04:  /* HSE used as system clock */

      SystemCoreClock = HSE_VALUE;

      break;

    case 0x08:  /* PLL used as system clock */

      /* Get PLL clock source and multiplication factor ----------------------*/

      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;

      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;

      pllmull = ( pllmull >> 18) + 2; // <<<<<<<<<<<<<<<< Why '+2' ?

      if (pllsource == 0x00)

      {

        /* HSI oscillator clock divided by 2 selected as PLL clock entry */

        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;

      }

      else....................

[KnarfB]

Hi, check the code with the reference manual for your chip, e.g. "RM0091Reference manual" for STM32F0x1/STM32F0x2/STM32F0x8:

in 6.4.2 Clock configuration register (RCC_CFGR) you find

"

Bits 21:18 PLLMUL[3:0]: PLL multiplication factor

These bits are written by software to define the PLL multiplication factor. These bits can be

written only when PLL is disabled.

Caution: The PLL output frequency must not exceed 48 MHz.

0000: PLL input clock x 2

0001: PLL input clock x 3

0010: PLL input clock x 4

...

"

You can see that the PLLMUL bits are extracted (RCC->CFGR & RCC_CFGR_PLLMULL)>>18 and the converted to the correct multiplication factor.

hth

KnarfB

[Kmax18]

Thank you for your answer! I see now that the purpose of adding 2 is matching the extracted 4-bit word to the listed multiplication factor. Thanks again.