Have anyone noticed a problem with the STM32L4 Wakeup Timer wakeup from standby with temperatures < -10°C?

[damh]

The Wakeup works fine with temperatures above. At a unit based limit the wakeup does not accure (only watchdog as fallback). RTC remains running.

Any ideas?

[waclawek.jan]

Provide as much information as possible about the circumstances - what's the power supply arrangement, and what clocks exactly are involved.

Possibly related? https://community.st.com/s/question/0D50X0000AwWhqcSQC/stm32l4-freezes-at-freezing-temperatures

JW

[Ozone]

Agree, I'm 99% sure the problem relates to the MCU's environment (power supply, clock source), and not the L4 itself.

[damh]

LSE 32768Hz

HSE 16MHz

PLL 80MHz

WATCHDOG 1s

Wakeup-Timer 500ms

Lowpower: standby with SRAM2-retention, backup-retention, RTC on

Power: STBB3JR-Stepup with target 3.3V in runmode, in standby: 3.3-3.4V battery (the problem remains, if the battery is OUTSIDE the climatic chamber)

@JW: it seems to be related, but my words for searching were different. We have many systems with the same L4 without any problems, but older than June/2019!

The problems seems to be statistical. If the system is cooling down. The first times it recovers by watchdog-reset. Over time it takes more watchdog-resets until it does NOT recover at some point.

We have tried to call "HAL_RTCEx_SetWakeUpTimer_IT()" twice or to only program it one time (at hardreset). With higher temperature it works in all versions. With lower in none.

[waclawek.jan]

You may want to start by reducing the firmware to bare minimum exhibiting the problem.

As @Viktor POHORELY​  said in that thread, try, one at a time, to 1. use HSI instead of HSE; 2. Avoid using PLL, 3. run code from SRAM.

JW

[damh]

The problem was an unused (but configured) PLLSAI1 with VCO=64MHz.

Errata says that "pll may not lock" as symptom, but that seams to be an euphemism.

[Ozone]

> Errata says that "pll may not lock" as symptom, but that seams to be an euphemism.

Since not every MCU showed the symptom, the "may" seems justified ... ;)

[Ozone]

> Errata says that "pll may not lock" as symptom, but that seams to be an euphemism.

Since not every MCU showed the symptom, the "may" seems justified ... ;)

[waclawek.jan]

Hi Johannes,

Thank you for coming back with the finding. This is very interesting - so one PLL influenced in some way the other?

So, finally, what did you do, did you just disable PLLSAI1 or did you set it to a higher VCO setting?

JW

@Viktor POHORELY​ 

[damh]

Tested with VCO_SAI1=96MHz and with disabled PLLSAI1. The unused RNG used the SAI1 as source and now PLLQ.

And as said before "the pll had no problem to lock", the system works fine. The problem accures at the moment you try to use "low-power"-modes.