Has a problem when using STM32F405 spi + dma as a slave

[CJi]

Use STM32F405's SPI + DMA as a slave, circular mode, DMA 16bytes interrupt, but every time send 16bytes to master, the first byte is always the byte that last frame's last byte , it looks like spi tx register is not clear, always contain the last byte, so my question is how can i avoid this problem?

[S.Ma]

The dma cyclic mode is different than fixed length.

It will always pre fill the tx before the current or last rx will be fully received. Once the transfer is cut by nss, the next byte is alreadt preloaded... If the dma was fixed length, the.end story would change. You can try to overwrite by prewriting again the tx data register before the sck clocks kicks in. Once you migrate to newer spi with fifo, you will discover that the tx fifo prevents overwriting the prefilled queue and can only be reset by spi reset. Disable won t work. So reset and reconfig fhe spi may not be so much of penalty. Init takes few microseconds... While Nss is high.

[TDK]

It looks like the first AA in the master receiver buffer is actually the last byte sent by the slave. You could increase buffer size to confirm. In which case likely the first byte the slave sends is something other than what you want, and gets overwritten by the AA at the end. Just not lined up. Prime the slave to send data before the CS line goes high.