2015-10-26 07:56 AM
Hello,
what is Half-cycle access (FLASH_ACR_HLFCYA) for? It may be used with slow clocks ( < 8 MHz) and AHB divisior = 1.2015-10-26 08:48 AM
Hi bonnes.uwe,
Half cycle configuration is not available in combination with a prescaler on the AHB. The system clock (SYSCLK) should be equal to the HCLK clock. This feature can therefore be used only with a low-frequency clock of 8 MHz or less. It can be generated from the HSI or the HSE but not from the PLL.-Syrine-2015-10-26 09:26 AM
Dear Syrine,
your response repeats what is written in the reference manuals. But is does not answer what Halfcycle access is good for!2015-10-26 09:55 AM
Hi bonnes.uwe,
Half Cycle Enable Access, if it is set, it halves the period during the flash signals are driven high to save power consumption.-Syrine-2015-10-26 02:10 PM
Syrine,
Thanks for your answer. Can this info be added to the relevant RMs, please? Is the upper bound to using this exactly 8MHz? Can this be clearly stated too? And can the power saving be quantified, best in the datasheet, please? Thanks Jan Waclawek