H723ZG Nucleo ADC clock/noise question

[Louie88]

After assembling the X3 external 25MHz crystal and 2 caps and generating initialize code for 550MHz clock with CubeMX my NUCLEO-H723ZG board runs fine, except ADC. It is very noisy. The CubeMX configured the clock for ADC = 96.000671 MHz (PLL2P). In the datasheet of the MCU the maximum ADC clock is 50MHz (BOOST=3) Is this okay or I found a bug in CubeMX?

I use ADC1 and ADC2 to sample two 150Hz 2Vpp sine wave signals. There is 100us phase difference between signals. (Blue is delayed) I start the ADCs simultaneously from TIMER1. When HAL_ADC_ConvCpltCallback() is called I read the ADC1 (yellow) and ADC2 (bule) conversion results. I generate the ADC1 – ADC2 signal with DAC1. Because the ADCs are in 16-bit mode but the DAC1 can handle 12-bit numbers only I right shift the ADC result by 4 and subtract the 12-bit numbers.

uint32_t difference = (chn1Data >> 4) - (chn2Data >> 4);

I write the value of difference variable into the DAC1. This is the green channel.

• Yellow: A signal (1V)
• Blue: B signal (1V)
• Orange: Comparator output (1V) It compares A input signal to +1.25V.
• Green: A-B signal on output of 12-bit DAC1 (100mV)

I also tried the 64-bit oversampling but it did not help or I configured something faulty:

  hadc1.Init.OversamplingMode = ENABLE;
  hadc1.Init.Oversampling.Ratio = 1 << 6;
  hadc1.Init.Oversampling.RightBitShift = ADC_RIGHTBITSHIFT_6;
  hadc1.Init.Oversampling.TriggeredMode = ADC_TRIGGEREDMODE_SINGLE_TRIGGER;
  hadc1.Init.Oversampling.OversamplingStopReset = ADC_REGOVERSAMPLING_RESUMED_MODE; 

With these settings I could get back the (integer) average of 64 ADC conversions of every sample point. Am I right?

Anybody has any idea why the difference signal so terrible?

Thanks,

Louis

[LCE]

Okay, the Nucleo-Boards are good enough for the digital part, but for the analog stuff, with the IO signals running wildly through the PCB, forget it...

You could download the PCB files (Altium, they have a viewer I think) and check the PCB traces, maybe you got some very bad IOs concerning routing as ADC inputs, and try some other input.

And you can solder at least a small cap to the input pin? LQFP144 is not that small. ;)

Or use another input access on the PCB, many IOs have solder bridges, these could be reset / set and used as a more direct input point.

Anyway, it looks like you're also using the ADC out of spec with that clock frequency, which might be another source for strange behavior.

So better stop relying on CubeMX and start using the ADC registers directly to make the necessary settings.

Check the peripheral clock going to the ADC and the prescaler / clock divider settings in the ADC registers. Change all that is out of spec.

[Louie88]

Yes, I would do this if I had my own custom board. We have no time for such a deep level debugging even for not our product. My job is to decide whether we can base our new transmitter on STM32H723ZG CPU or not.

So the best would be to get an WORKING ADC example DEDICATED to H723-NUCLEO board. Unfortunately there is a single LL analog watchdog example which is useless for me.

The input signal is from our 15 years old transmitter based on Silicon Labs C8051F060 8-bit CPU. I use the signals from the old transmitter in NUCLEO board. The old CPU's built-in 16-bit ADC converters convert crystal clear difference signal compared to NUCLEO board's signal. (From the same input signals)

I believe this is still a configuration bug in NUCLEO code. This is why an example would be nice. I know there are ADC examples for other boards and I learned a lot of from those examples but those cannot be used without code mods.

Thanks,

Louis

[Pavel A.]

ADC clock config issues in CubeMX/IDE:

https://community.st.com/s/question/0D53W00001VvUQLSA3/stm32cubeide-19-hal-fails-to-enable-adc-in-stm32h743vit6-revision-v

[Louie88]

Thanks Pavel for the link. I will check it.

Louis