H7 series FMC question

Hi, I am using STM32H725 with the FMC interface and trying to clarify some issues.

The initial issue was seeing extra writes/reads on the bus - this seemed to be fixed by switching the banks to use the 0xC...0 address range or configuring the original bank with the MPU.

After this we can only use 32 bit aligned addresses, i.e 0,4,8 etc and always see two accesses even if using HAL_SRAM_Write_16b with a buffer size of 1.

According the the reference manual

When AXI transaction data size is different from the device data width, the result depends on the following factors: • AXI transaction data size is greater than the device data width: – Read/Write transactions: the FMC splits the AXI transaction into smaller consecutive accesses matching the external device data width.

So, am I right in thinking that accesses are always 32 bits and on the second access A0 will go high?