GPIO Latency STM32F411 Blackpill

[vbesson]

Hello All, 

I am doing this post after trying everything I can to solve my Issue. 

I have a STM32F411 Blackpill connected on an Apple II Bus Slot.

The Apple II has a clock (Phi0) close to 1 Mhz. Phi0 is connected to Pin A2 where I have setup a Falling & Rising Edge interrupt. 

The GPIO B12 is used to check the latency between each Phi0 phase,

- at the falling edge of Phi0 B13 is clear

- at the rising edge of Phi0 B13 is set, 

I have nothing else running on this STM32, I am observing a delay (avg 335 ns) between the interrupt detection and GPIO set or clear.

Using the logic analyzer: 

Debug2 is the GPIO B13

I use the following code :

#define GPIO_SET_PIN(port, pin)       ((port)->BSRR = (pin))
#define GPIO_CLEAR_PIN(port, pin)     ((port)->BSRR = (pin << 16u))

#pragma GCC push_options
#pragma GCC optimize ("-Ofast")

void EXTI2_IRQHandler(void){
    __HAL_GPIO_EXTI_CLEAR_IT(PHI0_Pin);
    if ((PHI0_GPIO_Port->IDR & PHI0_Pin)==0){
      GPIO_CLEAR_PIN(DEBUG1_GPIO_Port,DEBUG1_Pin);    
    }else{
      GPIO_SET_PIN(DEBUG1_GPIO_Port,DEBUG1_Pin); 
    }
}
#pragma GCC pop_options

 The clock setting :

void SystemClock_Config(void)
{
  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};

  /** Configure the main internal regulator output voltage
  */
  __HAL_RCC_PWR_CLK_ENABLE();
  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);

  /** Initializes the RCC Oscillators according to the specified parameters
  * in the RCC_OscInitTypeDef structure.
  */
  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
  RCC_OscInitStruct.PLL.PLLM = 25;
  RCC_OscInitStruct.PLL.PLLN = 384;
  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4;
  RCC_OscInitStruct.PLL.PLLQ = 8;
  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
  {
    Error_Handler();
  }

  /** Initializes the CPU, AHB and APB buses clocks
  */
  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;

  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
  {
    Error_Handler();
  }
}

 The GPIO Settings:

static void MX_GPIO_Init(void)
{
  GPIO_InitTypeDef GPIO_InitStruct = {0};
/* USER CODE BEGIN MX_GPIO_Init_1 */
/* USER CODE END MX_GPIO_Init_1 */

  /* GPIO Ports Clock Enable */
  __HAL_RCC_GPIOC_CLK_ENABLE();
  __HAL_RCC_GPIOH_CLK_ENABLE();
  __HAL_RCC_GPIOA_CLK_ENABLE();
  __HAL_RCC_GPIOB_CLK_ENABLE();

  /*Configure GPIO pin Output Level */
  HAL_GPIO_WritePin(GPIOC, GPIO_PIN_13, GPIO_PIN_RESET);

  /*Configure GPIO pin Output Level */
  HAL_GPIO_WritePin(GPIOA, D_CE_Pin|D_DIR_Pin|IRQ_DRV_Pin, GPIO_PIN_RESET);

  /*Configure GPIO pin Output Level */
  HAL_GPIO_WritePin(GPIOB, DEBUG1_Pin|DEBUG2_Pin|A_CE1_Pin|A_CE2_Pin, GPIO_PIN_RESET);

  /*Configure GPIO pin : PC13 */
  GPIO_InitStruct.Pin = GPIO_PIN_13;
  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
  GPIO_InitStruct.Pull = GPIO_NOPULL;
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
  HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);

  /*Configure GPIO pins : RW_Pin DEVSEL_Pin */
  GPIO_InitStruct.Pin = RW_Pin|DEVSEL_Pin;
  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
  GPIO_InitStruct.Pull = GPIO_NOPULL;
  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);

  /*Configure GPIO pin : PHI0_Pin */
  GPIO_InitStruct.Pin = PHI0_Pin;
  GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING_FALLING;
  GPIO_InitStruct.Pull = GPIO_PULLUP;
  HAL_GPIO_Init(PHI0_GPIO_Port, &GPIO_InitStruct);

  /*Configure GPIO pins : D_CE_Pin D_DIR_Pin IRQ_DRV_Pin */
  GPIO_InitStruct.Pin = D_CE_Pin|D_DIR_Pin|IRQ_DRV_Pin;
  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
  GPIO_InitStruct.Pull = GPIO_NOPULL;
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);

  /*Configure GPIO pins : SD_EJECT_Pin RESET_Pin */
  GPIO_InitStruct.Pin = SD_EJECT_Pin|RESET_Pin;
  GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
  GPIO_InitStruct.Pull = GPIO_NOPULL;
  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);

  /*Configure GPIO pins : DA0_Pin DA1_Pin DA2_Pin DA3_Pin
                           DA4_Pin DA5_Pin DA6_Pin DA7_Pin */
  GPIO_InitStruct.Pin = DA0_Pin|DA1_Pin|DA2_Pin|DA3_Pin
                          |DA4_Pin|DA5_Pin|DA6_Pin|DA7_Pin;
  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
  GPIO_InitStruct.Pull = GPIO_NOPULL;
  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);

  /*Configure GPIO pins : DEBUG1_Pin DEBUG2_Pin */
  GPIO_InitStruct.Pin = DEBUG1_Pin|DEBUG2_Pin;
  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
  GPIO_InitStruct.Pull = GPIO_NOPULL;
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);

  /*Configure GPIO pins : A_CE1_Pin A_CE2_Pin */
  GPIO_InitStruct.Pin = A_CE1_Pin|A_CE2_Pin;
  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
  GPIO_InitStruct.Pull = GPIO_NOPULL;
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);

  /* EXTI interrupt init*/
  HAL_NVIC_SetPriority(EXTI2_IRQn, 0, 0);
  HAL_NVIC_EnableIRQ(EXTI2_IRQn);

/* USER CODE BEGIN MX_GPIO_Init_2 */
/* USER CODE END MX_GPIO_Init_2 */
}

Why do I have a huge latency between B13 & PHI0 ?

What can I change / do to reduce that gap ? 

Thank 

Vincent

[TDK]

Here are all the instructions it's doing after the IRQ fires but before GPIO is actually set.

 465              	EXTI2_IRQHandler:
 474 0000 0E4B     		ldr	r3, .L18
 475 0002 5B69     		ldr	r3, [r3, #20]
 477 0004 13F0040F 		tst	r3, #4
 478 0008 16D0     		beq	.L15
 480 000a 0C4B     		ldr	r3, .L18
 481 000c 0422     		movs	r2, #4
 482 000e 5A61     		str	r2, [r3, #20]
 485 0010 03F54443 		add	r3, r3, #50176
 486 0014 1B69     		ldr	r3, [r3, #16]
 488 0016 1340     		ands	r3, r3, r2
 490 0018 094A     		ldr	r2, .L18+4
 491 001a 1370     		strb	r3, [r2]
 494 001c 1378     		ldrb	r3, [r2]	@ zero_extendqisi2
 496 001e 3BB9     		cbnz	r3, .L17
 498 0020 03F18043 		add	r3, r3, #1073741824
 499 0024 03F50133 		add	r3, r3, #132096
 500 0028 4FF08052 		mov	r2, #268435456
 501 002c 9A61     		str	r2, [r3, #24]

18 instructions, 1-3 cycles each. You see an average of 21 cycles (+12 for ISR fire). Seems reasonable. Why does that seem strange?

[KnarfB]

You can switch to register level using CMSIS header files. Like so (not nested)

void EXTI2_IRQHandler(void) {
    // Check if the interrupt is triggered for PA2
    if (EXTI->PR & EXTI_PR_PR2) {
        // Clear the pending bit
        EXTI->PR = EXTI_PR_PR2;

        // Handle the interrupt (toggle an LED, etc.)
        GPIOA->ODR ^= GPIO_ODR_OD5;
    }
}

But, even if you could reduce the latency considerably, the throughput of 1M interrupts/s will render the CPU nearly useless for anything else. What do you intend to achieve?

hth

KnarfB

[vbesson]

I am working on a Apple II extension Card, 

I use a similar design as the one that use the Raspberry Pico (Dual core Cortex M0 133 MHz)

My goal is to provide to the data port the content of a ROM 2Kbytes

So within a CPU cycle : 

Set the Buffer to get the Adresse on the Bus, gather 2 x 74LS245 

Check the address and set PORTB to output, et write the GPIO the content of the Rom

It is quite basic, it is working on a RP2040, I assume I can do the same on a F411

[KnarfB]

You could poll Phi0 at A2 in a main loop and execute little code when a edge was detected. No interrupts.

hth

KnarfB

[waclawek.jan]

> It is quite basic, it is working on a RP2040, I assume I can do the same on a F411

The RP2040 may use its programmable PIO unit together with DMA, or any other hardware resource, to achieve this effect.

JW

[vbesson]

Hello Jan, 

Exactly this is what I have read in the datasheet, the RP2040 is ale to manage a 8.6 ns gap...

Is there a STM product (cheap) be able to achieve the same results ? 

Vincent 

[waclawek.jan]

I don't think there is any STM32 containing hardware which could effectively emulate a parallel memory.

JW