FSMC synchronous burst

[christopher2399]

Posted on November 07, 2011 at 12:25

Does anyone have any references for design articles or documentation - beyond the obvious manuals - for operating the FSMC in synchronous burst mode? I have seen AN2784, but this only deals with asynchronous memories.

Specifically, I am trying to design an interface between the STM32F207 and BRAM elements in a Xilinx FPGA. The BRAMs have a synchronous interface which looks a good match for the FSMC in PSRAM mode. I am trying to fill in the time while I wait for my prototype hardware by writing the VHDL to implement this interface in the FPGA, so I cannot as yet experiment with the hardware. Pages 121 to 126 in the User Manual show the timings for various operations on the synchronous bus. They all show a burst of two accesses. This begs the following questions: 1) Are there always two accesses in burst mode, or can there be just one (eg if a 16-bit write is made to external memory), or more (eg if there is a burst of accesses to adjacent addresses)? 2) What is the function of the byte lane signals in burst mode? They are shown as active in the timing diagrams, so can I assume that the synchronous mode is capable of single byte writes, using a burst length of one, and asserting just one of the byte lane signals? 3) If the number of accesses in a burst is variable, which signal from the STM32 to the memory indicates the end of the burst? All of the control signals (specifically, FSMC_NWE, FSMC_NOE, FSMC_NEx, FSMC_BLN) appear to become inactive one FSMC_CLK cycle too late to perform this function. For a burst of length N they are de-asserted on a clock edge after the one on which the (N+1)th transaction would occur. Any information gratefully received. CH == #stm32-fsmc

[christopher2399]

Posted on November 11, 2011 at 11:24

I have now discovered several incoinsistencies between the data sheet pp121-125 and the user manual pp1245-1256. In summary, I think the User Manual cycle diagrams are more likely to be correct, as they seem to describe a bus that is actually usable!

In summary: 1) Figures 57 and 59 in the data sheet both show waveforms for BUSTURN=1, even though they are labelled BUSTURN=0. There is an extra FSMC_CLK cycle between the final READ on the bus and NEx being deasserted compared with figure 412 in the User Manual. 2) Figures 58 and 60 in the data sheet are also labeled BUSTURN=0, and both show an extra cycle between the final WRITE and NEx being deasserted, compared with figure 413 in the User Manual. This appears to be plain wrong, as extra BUSTURN cycles are never instered in WRITE transactions (User Manual, page 1254). 3) The role of the byte lane signals is still a bit vague, but it would appear sensible if they allowed a burst of length 1 to transfer a single byte, as they do when using the bus in asynchronous mode. CH ==

[christopher2399]

Posted on November 11, 2011 at 11:41

Sorry to reply to my own post again, but I now discover that BUSTURN cycles can indeed appear at the end of write bursts (user manual p 1256). However, the cycle diagrams in the data sheet are still wrong, as they all show an extra cycle with NEx asserted, whereas the extra BUSTURN cycles are instered with NEx de-asserted, as far as I can tell.