FSMC - Multiplexed vs Non-Multiplexed mode on LQFP100 packages

[Zaher]

I have used the FMC successfully in several projects to memory-map certain devices in a Non-Multiplexed mode where separate data and address lines are assigned. On devices with smaller package (e.g., STM32F407) the FSMC is only available in multiplexed mode where address signals are multiplexed with data bus. To keep space and budget low for the target board, I'm considering replacing the STM32F429 with the STM32F407. However, there are certain ambiguities surrounding the FSMC/addressing for me and I would like to hear from you guys before I go any further.

As you know, the FSMC can be configured only for multiplexed mode for PSRAM/NOR devices in CubeMX, but address lines (FSMC_A16 ~ FSMC_A23) are still available in the pinout view. What is the purpose of these lines if the address data is multiplexed on the data bus? What happens when assigned from within the CubeMX? Why they are not shown in the left pane (mode/configuration) of the FSMC peripheral?

I have found this article here explaining the FSMC in detail:

https://programmersought.com/article/66384511566/

But I didn't understand why and how A16~A23 are used here in multiplexed bus where signals are assigned as FSMC_DAx? Same also goes for the data signals, they can be changed in CubeMX from FSMC_DAx to FSMC_Dx, but what happens if I changed them and disabled multiplexing in code? In other words, can I use the STM32F407 in non-multiplexed mode?

I know a logic analyzer might help to reveal a lot, but unfortunately, I don't have access to one at the moment.

Zaher

[waclawek.jan]

The high portion of address is output onto A16-A23 during the whole read/write cycle.

The low portion of address i.e. A0-A15 is output to DA0-DA15 the first half of the read/write cycle, and you have to latch it using the NADV=NL signal. Then, in the second half of read/write cycle, data are read/written on DA0-DA15.

JW

[Zaher]

Thank you for the explanation. So, the higher portion of the address is always output on A[16.23]. OK, given that the ASIC I'm interfacing has only 4-bits of addressing and allows for multiplexed bus transactions, in this case I suppose the address data will be latched on the first 4 DA bits (upon activating Address-Valid signal) and nothing will be output on the A[16.23] lines, right?

[waclawek.jan]

Do you need the external memory area as viewed from the processor to be continguous?

If not, i.e. if you are going to access it as 16 separate "registers", you may as well avoid using the multiplexed mode entirely. You would then simply use the simplest straightforward "SRAM" mode, use e.g. A16..A19, and access the "registers" at addresses 64kB apart, e.g. first "register" at 0x6000'0000, second at 0x6001'0000, etc.

Whether this is viable, of course depends on your particular application.

JW

[Zaher]

No, I'm interfacing an ASIC so I need to basically read/write a set of registers on a random basis. Of course, this sounds viable for the intended application, but I thought it's not possible to use the FSMC on F407 in non-muliplexed mode. I hope I did not get you wrong!