Hello,
We have been using two SRAMs (CY7C1061G30-10BV1XE) & one NAND Flash(MT29F8G08ADAFAH4-AAT) interfaced with STM32L562 micro-controller on same FMC bus. We have initialised FMC and try to access SRAM1 by selecting Chip select: NE1 and Bank 1. It is being observed that there is mismatch between Read and Write Data in Bank 1 (FMC Base address: 0x60000000). Also, we have tried to change the various parameters' values as configurable under FMC Initialisation (like: Byte Lane NBL set-up timing and other SRAM timing parameters), but this all could not help us and data mismatch persists. Also, we suspect that FMC clock frequency which is set as 25MHz in our case.
Schematic of SRAM, our code and FMC initialisation can be referred below:
(1) FMC_Initialisation:
static void MX_FMC_Init(void)
{
/* USER CODE BEGIN FMC_Init 0 */
/* USER CODE END FMC_Init 0 */
FMC_NORSRAM_TimingTypeDef Timing = {0};
/* USER CODE BEGIN FMC_Init 1 */
/* USER CODE END FMC_Init 1 */
/** Perform the SRAM4 memory initialization sequence
*/
hsram4.Instance = FMC_NORSRAM_DEVICE;
hsram4.Extended = FMC_NORSRAM_EXTENDED_DEVICE;
/* hsram4.Init */
hsram4.Init.NSBank = FMC_NORSRAM_BANK1;
hsram4.Init.DataAddressMux = FMC_DATA_ADDRESS_MUX_DISABLE;
hsram4.Init.MemoryType = FMC_MEMORY_TYPE_SRAM;
hsram4.Init.MemoryDataWidth = FMC_NORSRAM_MEM_BUS_WIDTH_16;
hsram4.Init.BurstAccessMode = FMC_BURST_ACCESS_MODE_DISABLE;
hsram4.Init.WaitSignalPolarity = FMC_WAIT_SIGNAL_POLARITY_LOW;
hsram4.Init.WaitSignalActive = FMC_WAIT_TIMING_BEFORE_WS;
hsram4.Init.WriteOperation = FMC_WRITE_OPERATION_ENABLE;
hsram4.Init.WaitSignal = FMC_WAIT_SIGNAL_DISABLE;
hsram4.Init.ExtendedMode = FMC_EXTENDED_MODE_DISABLE;
hsram4.Init.AsynchronousWait = FMC_ASYNCHRONOUS_WAIT_DISABLE;
hsram4.Init.WriteBurst = FMC_WRITE_BURST_DISABLE;
hsram4.Init.ContinuousClock = FMC_CONTINUOUS_CLOCK_SYNC_ONLY;
hsram4.Init.WriteFifo = FMC_WRITE_FIFO_ENABLE;
hsram4.Init.NBLSetupTime = 0;
hsram4.Init.PageSize = FMC_PAGE_SIZE_NONE;
hsram4.Init.MaxChipSelectPulse = DISABLE;
/* Timing */
Timing.AddressSetupTime = 2;
Timing.AddressHoldTime = 2;
Timing.DataSetupTime = 2;
Timing.DataHoldTime = 2;
Timing.BusTurnAroundDuration = 2;
Timing.CLKDivision = 16;
Timing.DataLatency = 17;
Timing.AccessMode = FMC_ACCESS_MODE_A;
/* ExtTiming */
if (HAL_SRAM_Init(&hsram4, &Timing, NULL) != HAL_OK)
{
Error_Handler( );
}
/* USER CODE BEGIN FMC_Init 2 */
/* USER CODE END FMC_Init 2 */
}
(2) FMC Defs (main.h):
#define SRAM_BANK_ADDR ((uint32_t)0x60000000)
#define WRITE_READ_ADDR ((uint32_t)0x0800)
(3) Code (main.c):
uint16_t txbuffer=0x1234;
uint16_t rx;
if(HAL_SRAM_Write_16b(&hsram4,
(uint32_t *)(SRAM_BANK_ADDR + WRITE_READ_ADDR),
&txbuffer,
sizeof(txbuffer)) != HAL_OK)
{
//return SRAM_ERROR;
printf("ERROR");
}
/* Read back data from the SRAM memory */
if(HAL_SRAM_Read_16b(&hsram4,
(uint32_t *)(SRAM_BANK_ADDR + WRITE_READ_ADDR),
&rx,
sizeof(rx)) != HAL_OK)
{
printf("ERROR");
// return SRAM_ERROR;
}
