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FMC/FSMC ECC computation

PMera.1
Associate II

Hello, guys!

I have a quick question about FSMC's ECC routine.

From what I understood, the workflow goes like this:

1) Enable ECC computation

SET_BIT(hnand->Instance->PCR, FMC_PCR_ECCEN);

2) Write data to the target device

3) Get the computed ECC

while (__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FEMPT) == RESET) ;
			uint32_t ecc = hnand->Instance->ECCR;

3) Disable ECC

CLEAR_BIT(hnand->Instance->PCR, FMC_PCR_ECCEN);

Rinse and repeat.

It works as expected, but with a small caveat: my NAND page size is 8kb + 448 bytes.

And, as per the FSMC's docs, it can generate an error correction code of up to 32 bits. These are clearly insufficient to provide more than error detection. Because of the huge page size, getting a 0-bit or 1-bit error is highly unlikely.

Because speed is somewhat of an issue, I can't really rely on software ECC computation, so I'm trying to "trick" the FMC peripheral into providing separate ECC bits for chunks of the written page, like so:

 
        uint16_t eccCounter = 0;
         
	for (index = 0U; index < PAGE_SIZE; index++) // PAGE SIZE IS 8 * 1024
	{
                // START THE ECC COMPUTATION
		if(eccCounter == 0)
		{
			SET_BIT(hnand->Instance->PCR, FMC_PCR_ECCEN);
		}
                // WRITE THE NEXT BYTE TO DEVICE
		*(__IO uint8_t *)deviceaddress = *buff;
		buff++;
		__DSB();
		if(eccCounter++ == 0xFF)
		{
                        // WAIT FOR ECC READY
			while (__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FEMPT) == RESET) ;
                        // GET GENERATED ECC
			uint32_t ecc = hnand->Instance->ECCR;
			debug_print("%08X | ", ecc);
                        // STOP ECC COMPUTATION
			CLEAR_BIT(hnand->Instance->PCR, FMC_PCR_ECCEN);
			eccCounter = 0;
		}
	}
	debug_print("\n");

So basically I'm trying to get the ECC for different chunks of the same page, whilst sending them to the device.

The FMC device ECC Page Size is set to 256 byte.

However, after the first ECC Computation, which yields a value, all subsequent values are 0.

Any kind of help would be greatly appreciated! Thank you!

2 REPLIES 2

ST hasn't supported this very much, it was designed in a day when the NAND sectors/levels were smaller, and ST owned a NAND business.

I don't think it's kept up with the MLC devices, and frankly the NAND devices started generating/checking syndrome bytes themselves.

You'd need to find an ST FAE with specific experience with NAND ECC, and the STM32 implementation, and perhaps the state-machine for the generation, and then flushing/checking phases.

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Thanks. I was hoping somebody hit the same brick wall as I did and had some kind of workaround. I haven't really managed to solve this issue. Yet.