EXTI minimal pulse length clarification

[waclawek.jan]

Posted on April 25, 2017 at 14:11

DS STM32F405xx STM32F407xx, DocID022152 Rev 8, Table 50. I/O AC characteristics :

tEXTIpw Pulse width of external signals detected by the EXTI controller  - min.10ns

This hints that there's a pair of edge-sensitive latches for each EXTI input, independent from any internal clock.

RM0090, DocID018909 Rev 13, 12.2.1  EXTI main features says otherwise:

The main features of the EXTI controller are the following:

[...]

detection of external signals with a pulse width lower than the APB2 clock period. Refer

to the electrical characteristics section of the STM32F4xx datasheets for details on thisparameter.

Max. APB2 clock is 84MHz so the period is >10ns; but regardless, the DS should not use a fixed value if it is APB-clock dependent.

ST, please clarify.

JW

[Uwe Bonnes]

Posted on April 25, 2017 at 15:30

For me the documentation sounds like EXTI edgedetection is not APB-clock dependent. But e.g. for the F76x DocID029041 Rev  

 2.14 External interrupt/event controller (EXTI)

 ...The EXTI can detect an external line with a

 pulse width shorter than the Internal APB2 clock period.

and Table 67. I/O AC characteristics(1)(2) (continued)

 tEXTIpw > 10 ns

contradict. ST, please clarify.

[Uwe Bonnes]

Posted on April 25, 2017 at 17:42

No Clive, I am quite sure the edge detection happens asynchronous to the internal clocks. Otherwise the tEXTIpw specification would have the clock in its formula...

[waclawek.jan]

Posted on April 25, 2017 at 16:37

Thanks Uwe for the comment. This clarifies it, at least for the 'F407: 10ns *is* shorter than APB2 period indeed - my bad.

I believe the 'min 10ns' is a requirement for the external signal source, i.e. the latch captures pulses shorter than 10ns.

Still, I'd love to know if there's an asynchronous latch indeed.

Jan

[Tesla DeLorean]

Posted on April 25, 2017 at 16:47

The GPIO on both the F4 and F7 are in the AHB clock domain, the pins are going to have a synchronizer circuit off the back-end of the schmitt trigger to pull them into that domain, and your view of GPIOx->IDR. They may then go into fractional, but synchronous, clock domains for the APB2 (EXTI), at which point the signal is surely guaranteed to be at least half the APB2 period in terms of hold time.

[Tomas DRESLER · Accepted solution]

Posted on May 05, 2017 at 20:30

The front-end is asynchronous. Very useful in STOP mode when internal oscillators are OFF :)

[waclawek.jan]

Posted on May 05, 2017 at 22:44

Ahoj,

Thanks, this is good to know.

Jan

[waclawek.jan]

Posted on July 10, 2017 at 13:38

One more question: where exactly are the EXTI inputs tapped off from the GPIO cell, before the Schmidt or after? In other words, would setting the GPIO to Analog switch off EXTI or not?

Thanks,

Jan