External SDRAM with STM32F767 Nucleo board

[AMerc.4]

Hello,

i bought this SDRAM and i connected it to my STM32F767 Nucleo board. My init function is

static void MX_FMC_Init(void)
{
 
  /* USER CODE BEGIN FMC_Init 0 */
 
  /* USER CODE END FMC_Init 0 */
 
  FMC_SDRAM_TimingTypeDef SdramTiming = {0};
 
  /* USER CODE BEGIN FMC_Init 1 */
 
  /* USER CODE END FMC_Init 1 */
 
  /** Perform the SDRAM1 memory initialization sequence
  */
  hsdram1.Instance = FMC_SDRAM_DEVICE;
  /* hsdram1.Init */
  hsdram1.Init.SDBank = FMC_SDRAM_BANK1;
  hsdram1.Init.ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_8;
  hsdram1.Init.RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_13;
  hsdram1.Init.MemoryDataWidth = FMC_SDRAM_MEM_BUS_WIDTH_8;
  hsdram1.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4;
  hsdram1.Init.CASLatency = FMC_SDRAM_CAS_LATENCY_3;
  hsdram1.Init.WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE;
  hsdram1.Init.SDClockPeriod = FMC_SDRAM_CLOCK_PERIOD_2;
  hsdram1.Init.ReadBurst = FMC_SDRAM_RBURST_DISABLE;
  hsdram1.Init.ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_1;
  /* SdramTiming */
  SdramTiming.LoadToActiveDelay = 2;
  SdramTiming.ExitSelfRefreshDelay = 8;
  SdramTiming.SelfRefreshTime = 4;
  SdramTiming.RowCycleDelay = 7;
  SdramTiming.WriteRecoveryTime = 3;
  SdramTiming.RPDelay = 2;
  SdramTiming.RCDDelay = 2;
 
  if (HAL_SDRAM_Init(&hsdram1, &SdramTiming) != HAL_OK)
  {
    Error_Handler( );
  }
 
  /* USER CODE BEGIN FMC_Init 2 */
 
  /* USER CODE END FMC_Init 2 */
}

but my memory manager doesn't read it. However, if i put into this function a custom user code such as

FMC_SDRAM_CommandTypeDef Command;
 
/* Step 1: Configure a clock configuration enable command */
Command.CommandMode            = FMC_SDRAM_CMD_CLK_ENABLE;
Command.CommandTarget          = FMC_SDRAM_CMD_TARGET_BANK1;
Command.AutoRefreshNumber      = 1;
Command.ModeRegisterDefinition = 0;
 
/* Send the command */
HAL_SDRAM_SendCommand(&hsdram1, &Command, 60);

i can read my SDRAM both at 0xC0000000 and 0xD0000000. However, if i put this code in the main

uint32_t *externalRAM = 0xC000000;
const uint32_t size = 1000;
 
//write external RAM
for(int i = 0; i < size; i++)
{
    externalRAM[i] = i;
}

i can't see any difference.

[berendi]

There is no minimum SDRAM clock frequency listed in the datasheet, but keep in mind that the refresh rate should be adjusted accordingly. See the description of the SDRAM Refresh Timer register (FMC_SDRTR) in the reference manual.

[AMerc.4]

I don't know what are the timing parameters to set with 10 MHz. I can find exit self refresh delay parameter in nanoseconds (70 ns) in the datasheet, which at 10 MHz is 1 clock cycle (right?). but tghe others?

[AMerc.4]

How can i attach it? Do you want only the main.c file?

[AMerc.4]

Yes i know that this is not the best way to cennect it. But i don't know any way to connect it to my nucleo board.

[AMerc.4]

This is the main.c file.

[MEdgerton]

Hi, I'm looking at adding sram to my nucleo-F767 to test some ideas.

Did you fix this as its always good to start from a known good design.

To confirm you are using IS42/45S16160J from your link?

I noticed the line hsdram1.Init.MemoryDataWidth = FMC_SDRAM_MEM_BUS_WIDTH_8;

But the device above is configured as ​4M x16x4 Banks. The other device on the dataset (not the part number you listed) appears to have an 8 bit data bus.

Does this explain the issue?

I look forward to hearing back.

Thanks,

Mark​

[AMerc.4]

Hello, i subsequently changed the sdram to one more supported by examples, like MT48LC16M16A2P

https://lcsc.com/product-detail/SDRAM_Micron-Tech-MT48LC16M16A2P-6A-IT-G_C26393.html

[MEdgerton]

Hi,

Thanks for the reply. I have actually just got the original device working and also have it mapped into normal IO space (so you don't have to make HAL calls to access it. I have ade it so it forces certain parts (data logging) to be stored in the external SDRTAM and the main in the on chip.

Interestlingly I managed over 100MHz with short lengths of wire (about 4cm) I wasn;t expecting that much speed. I havent had time to push it further as PCB next.

I did run many tests on it and could demonstrate they caused a fail properly when expected.

I see the part you listed has less space, and have you links to the examples you mention for future reference.

If you'd like to know more of what I have done, please ask!

Mark

[SGajw.1]

@MEdgerton​ How do you manage the memory across internal SRam vs external SDRam? Are you managing the pool yourself through a global allocator which allocates on the bank needed? Or if there any OS (FreeRTOS) configuration that can be set?