Expereincing watchgog reset issue while machine is running.

[asth_raj]

Hello everyone,
I'm currently working with the "STM32G0B1RE" and facing an issue where my system automatically resets. The problem occurs sporadically, sometimes after a week and other times within 2 or 3 hours. Upon investigating, I found that the last reset cause is due to a watchdog timeout. Unfortunately, connecting a debugger is not feasible. Is there a method to store information about which instruction or address triggers the watchdog timeout?

Thanks & Regards,
Raj Asthana.

[Peter BENSCH]

Welcome @asth_raj, to the community!

Unfortunately, you have not provided any information on how you have programmed which watchdog (there are two: IWDG and WWDG). I suspect that the IWDG triggers the reset in your case, possibly because its clock frequency drifts away due to thermal influences. In general, the IWDG is clocked by the free-running LSI, the frequency of which has a fairly large tolerance that needs to be taken into account. For an initial test, you could increase the IWDG timeout by 10...20%.

Hope that helps?

Regards
/Peter

[Sarra.S]

Hello @asth_raj, 

Please check this monthly newsletter, to be aware of known IWDG limitations. 

[TDK]

> Is there a method to store information about which instruction or address triggers the watchdog timeout?

There is no method to do this after reset, but before reset you could implement an early wakeup interrupt (EWI) for the WWDG and store the information  from there to be read out after the reset. There is no such EWI mechanism for the IWDG on this chip.