I have a custom designed board using a STM32F429IET6 and LAN8742A.
While attempting to bring-up ethernet and LWIP (fails w/o LWIP at the same spot) the code continuously fails in stm32f4xx_hal_eth.c in `HAL_ETH_Init` while waiting for the SW reset to complete after setting the SR bit in the DMABMR register.
I've attempted copying as closely as possible the development board design (Nucleo-F429ZI) in software. The only differences that I can see are:
- We use PG14 for RMII TXD0 instead of PB13.
- We are using a 25MHZ external clock instead of the 8MHZ the Nucleo-F429ZI uses, but both running the board HCLK @ 168MHZ.
- We use a dedicated reset line from the MCU PA6 to the nRST line on the LAN8742.
- The Nucleo has the RXER pin going through a 10k then to GND. We also have a 10k to GND but it also ties to PB10. Currently, we have the PB10 pin not setup.
This is where the timeout is happening in stm32f4xx_hal_eth.c (see line 15 of this snippet):
/* Ethernet Software reset */
/* Set the SWR bit: resets all MAC subsystem internal registers and logic */
/* After reset all the registers holds their respective reset values */
SET_BIT(heth->Instance->DMABMR, ETH_DMABMR_SR);
/* Get tick */
tickstart = HAL_GetTick();
/* Wait for software reset */
while (READ_BIT(heth->Instance->DMABMR, ETH_DMABMR_SR) > 0U)
{
if (((HAL_GetTick() - tickstart) > ETH_SWRESET_TIMEOUT))
{
/* Set Error Code */
heth->ErrorCode = HAL_ETH_ERROR_TIMEOUT;
/* Set State as Error */
heth->gState = HAL_ETH_STATE_ERROR;
/* Return Error */
return HAL_ERROR;
}
}
Below is a screenshot of the clock configuration:
When we probe the ETH_REF_CLK we see the line go high, clock for a small amount of time at the wrong frequency (~1.25khz) and then remain high afterwards.
