I have 2 boards, basically identical except one has PHY KSZ8091RNA and the other has KSZ8091RND.
Both use the STM32F429NIH6.
The only difference I can find in the two PHYs is that I need to set to set the REFCLOCK bit in KSZ8091RNA's PHYC2 register. With that bit both boards detect link properly.
The KSZ8091RND board works, can transmit and receive Ethernet frames.
The KSZ8091RNA board locks up when I try to flush the transmit FIFO by setting the FTF bit in the DMAOMR register.
It is supposed to reset the transmit controller FIFO logic and be automatically cleared.
It never gets cleared, and the MAC never receives or transmits any packets.
I'm writing to the DMAOMR register and not writing again until that bit is cleared.
With the KSZ8091RND the bit is cleared immediately.
I verified that all registers are identical up until that point with the two PHYs, except for the REFCLOCK bit.
The receive descriptors are set up and owned by hardware.
What could be blocking the transmit FIFO Flush?
