ESP-PSRAM64H and STM32H743 QSPI mode

[Dat Tran]

Hi,

Is there any one success with ESP-PSRAM64H in memory mapped mode?

We are able to read ID (0x9F) in spi mode. But when we read/write, it return 0xFF. We don't see EnableWrite command, does this chip has EnableWrite command?

We also wanted to use this memory as RAM so we can read and write from a pointer.

But how we send Read and Write command Id at the same time when set register at memory mapped mode?

Many thanks

[Tesla DeLorean]

Related topics, easier for me to find later

https://community.st.com/s/question/0D53W00000iCq1hSAC/stm32h723-problem-with-serial-ram-in-memory-mapped-mode

[APiro.1]

Tesla DeLorean,

Thanks for sharing of the link! It seem that we need to try the APS6408L-3OBM-BA to see if it works. It may wait until next version of our prototype board to add it on, because I couldn't find any evaluation board of this BGA.

/Artin

[Alex - APMemory]

Hi,

I'm not sure which board you are looking at. For reference, we did test APS6408L-3OBM-BA  on MB1331 for STM32H7A/B, by replacing the NOR to IoT RAM using the OCTOSPI2 slot. Demo code attached as well.

Thanks

Alex

[Alex - APMemory]

Hi Artin,

Please see APS6408L-3OBM-BA code example attached, It was used on MB1331 STM32H7A/B board, replacing the NOR by our RAM on the OCTOSPI2 slot

Hope this help

Alex

[APiro.1]

Hello Alex,

Thanks for description and the sample code! I really appreciate it. We are going to produce a new version of prototype board for one of our new products and I will add APS6408L-3OBM-BA on it to test.

What I meant by evaluation board was that if APM had small PCBs with APS6408L-3OBM-BA like in your picture. It would help people to verify the memory with their designs and APM to sell more memory.

/Artin

[TimDunn]

I'm looking for a processor beyond the H743 that can support Memory Mapped Write function to a QSPI SRAM or possibly a 12 pin PSRAM of at least 32Mbits.   I'm having trouble confirming that the FMC can support the 12 pin PSRAM in HyperBus (see Infineon S27KL0642DPBHI020).

Will the FMC Memory Mapped Read and Writes respect the HyperBus RDWS line and the needed command interface? 

From CubeMX with the H743, the FMC signals are CLK, NOE, NWE, NWAIT, NL, NE1, plus the 8 data lines.  If there is any hope of this working, it appears the NWAIT would need an inverted sense of RDWS from the PSRAM.

If the choice is another processor, I need the 2MB Flash, 1MB RAM, Ethernet MAC, along with a UART.  To fit on my PWB, I need a BGA100 at 0.8mm pitch.  It looks like the H7Ax/Bx you mentioned above are missing the Ethernet MAC.

Any suggestions?