2024-06-17 08:48 AM
Do any of the Cortex M4 or M33 based MCUs have ECC on the processor's registers?
If not, is there a mechanism built into the processor to ensure that processor registers (R0, R1, R2...R15 etc) are not corrupted due to SEU?
Regards,
Hamid
2024-06-17 08:56 AM
No
Perhaps look at using something that's error-resistant, fault-tolerant or space-rated rather than expect commercial-off-the-shelf to carry this level of protection
SPARQ Leon 3 ?
2024-06-17 09:52 AM
Thanks.
This is an application that can be done reliably and comfortably in a 4x4mm Cortex M0+ based STM32L0 or STM32U0 processor.
Unfortunately, the client is working to meet a spec, based on a spec, that is based on a spec... and they all come together to impose this requirement on just this one module in the fairly large system.
The client already has a solution. I think it is based on a Cortex-R based MCU -- I am not sure. But that option is too big. I am tasked with finding a physically smaller solution. Otherwise, they will stick with the existing solution and deal with the size penalty.
Thanks,
Hamid