Does the STM32F722IE FMC block support multiplexed, 32-bit data width SRAM-like interface?

[CHahn.1]

I have an application that requires a high speed interconnect between a large FPGA and STM32F7 microcontroller. We chose to use the FMC block for memory mapped access into our FPGA. Does the FMC block in the STM32F7 support 32-bit data width with multiplexed address? Nothing in the technical reference manual explicitly forbids 32-bit multiplexed, but the device pinout does not have a "multiplexed" FMC_DAx pin where x > 15. It does however have FMC_Dx where x is in range [16, 31]. I thought this was suspicious - hence I ask here.

Many thanks

[waclawek.jan]

The FMC/FSMC documentation is generally very poor. I would expect if you set MWID to 32-bit and MUXEN to 1, that you'd see the lower 16 bits to be multiplexed on the DAx pins, whereas data and addresses above 16 would work through their dedicated pins.

As this is not explicitly documented, I would experiment first with a Nucleo or similar board, and/or contact ST directly.

JW