Does HAL_QSPI_AutoPolling respect Dual Flash Mode configuration?

[JHedges]

Hi,

I have an application of which uses the STM32F469NI with two MX25L12833F QSPI flash in dual flash mode and are encountering an issue when using HAL_QSPI_AutoPolling().

CLK is configured at 1MHz (to allow for logic analyser), both devices share the same CLK and nCS lines, where nCS is provided from BK2_nCS.

When performing a sector erase, the instruction is sent to both chips as outlined in AN4760 section 2.2.4, the peripheral is then configured to auto poll for the WEL and WIP bits to be reset. I am seeing that it does not respect both chips. The device on QSPI1 can finish and the autopoll stops yet the device on QSPI2 continues the erase operation. See attached snippet from a logic analyser where device 1 is CH2-5 and device 2 is CH6-9.

Is this expected behaviour or is extra configuration required for autopolling when using Dual Flash mode?

Thanks,

Jack

[Tesla DeLorean · Accepted solution]

The byte request length should be set to two, and the match/mask as 16 bits wide where the status bits are put in both high and low bytes.

Have dual configuration here where mass erase in first chip a lot quicker than second, so the 2 bytes read, mask, compare forces both to be considered.​

[JHedges]

Thankyou very much! That has sorted it, unfortunately that isn't too clear from what is otherwise excellent documentation!

[Tesla DeLorean]

The common command and interleaving of bytes takes some getting ones head around, especially when reading/writing multiple registers.

Some of this could perhaps have been better rolled into the QUADSPI library code, as from the outset it configures the interface in dual mode.