Does DQSM need to be enabled when stm32H7 connects to PSRAM?

[Lin_Yishan]

Thank you for reading.

I am trying to use the STM32H735 for PSRAM memory reading and writing. The PSRAM model is ISS66WVO32M8DBLL.
In all the materials I read, it is stated that DQS should be enabled. But in fact, when I set it this way, it will make the data offset more severe, which is why?

The situation is as follows:
Use indirect mode to write 16 numbers to PSRAM memory, then read, when I disable DQSM, read data offset by 1 bit, the first data read more than once, the last data was chipped off; When I enabled DQSM, the data shifted even more, and there were even problems of data overread and misread. The change of address and the data volume phenomena are consistent, so I have reason to doubt whether the bit can be aligned when reading the data?

Below I will provide my key code, thank you for helping to answer questions!

[KDJEM.1]

Hello @Lin_Yishan ,

Could you please take a look at the STM32H735 errata sheet and check the different conditions for DQS configuration and the workaround:

• 2.8.5 Data not sampled correctly on reads without DQS and with less than two cycles before
  the data phase 
• 2.8.8 Single-, dual- and quad-SPI modes not functional with DQS input enabled
• 2.8.9 Additional bytes read in indirect mode with DQS input enabled when data length is too short

Also could you please refer to memory datasheet and check the dummy cycle.

May this discussion can help you Solved: External Flash downloader shift 1 byte in flash ar... - STMicroelectronics Community 

I hope this help you!

Thank you.

Kaouthar