Do any STM32 devices support 20-bit SPI?

[Uwe Bonnes]

U5 has also 32 bit SPI.

[tjaekel]

U5 has 4..32bit!

reference manual, page 2888, 68.2:
"From 4- up to 32-bit data size selection or fixed to 8-bit multiples"

page 2904:

As I understand:

• 20bit should be directly possible (or even as 5x 4bit, 2x 10bit)
• Just: not all SPIs are "full feature"

[tjaekel]

BTW:

even SPI would not support 20bit word size - but MCU would provide a QSPI - the 20bit is possible via QSPI - but just as transmit only ("half-duplex"):

Configure a QSPI as 4-bit-lane but you use just one lane (only DIO0 = MOSI, for instance, is connected). Now you have two clocks per one byte. But you send all bits properly encoded in bytes (e.g. bit 0 and bit 4 Tx containing data bit 0, bit 1, etc.).

Now you have Nx 2 clocks (2 bits) you can send.

Just: such a QSPI is not full-SPI: it cannot run in "full-duplex" mode (MOSI and MISO at the same time). As long you need just a SPI Tx - you can use also a QSPI peripheral.
(but I think you need SPI in "full-duplex", Rx when Tx - so, find MCU with 4..32bit SPI and configure it properly)

[SoCalJim]

Thanks! :)

[SoCalJim]

I forgot to mention that I'm listening to communication between two other devices, so I have to be slave.

The QSPI discussion is valuable for the other end of translator I'm  making though. Thanks!

[tjaekel]

If you need just a slave (only Rx) in order to monitor (listen to) two external devices sending 20bit "words" between each other - you could also use an SAI, like an I2S/TDM slave device (with 20bit frame length).

If these two devices communicate permanently, means: there are always 20bit words exchanged, you could even listen with a 32bit word size configured slave: just to be aware that SPI slave will be "complete" after 32bit, so 20bit + 12bit (as part of next 20bit word transmission). So, Monitor Slave SPI is a bit behind. The SW can take 20bits for previous word, keep the 12bit already received, wait for the next 20bit plus 12bit (shift and combine together with already received 12bit) ... and extract the 20bit words from a stream "as 32bit" (stored as a stream of 32bit words in memory).

Do you want to build a SW based Logic Analyzer (sample a bit sequence with a CLK signal)?
And you want to add a "word decoding" (as 20bit) afterwards (when you have the stream of bits in memory?

Where is the problem?

You could also sample:

• 5x 32bit words = 160bit
• which corresponds to 8x 20bit words
• after 5x Rx done - you have 8 words available and you can display the results

Only problem: when you do not "monitor" also nCS signal between these two devices - you do not know where these 20bit word start. You need any other "reference" signal (such as nCS) in order to know where you are in a stream of bits.

So, a Slave Rx but using HW nCS signal, to be in sync! (SPI Slave using also nCS as HW input signal, on SAI this nCS signal acts like LRCK).
Or: use nCS falling edge as an INT to "release" your SPI Rx (for the next 5x 32bit words) - assuming the gap between nCS falling edge and first clock edge is large enough - potentially tough.

To analyze the requirements and break it down, to elaborate which building blocks needed, looking for options and to synthesize a system afterwards makes it easier to implement a working system. Your question about "20bit possible with MCU SPI" is part of the elaboration and just one option. Often several options possible to come up with a solution.

Good luck.