DMA With TIM3

[sanju]

Posted on May 03, 2018 at 13:24

Waclawek.Jan

‌

ELMHIRI.Syrine

‌

Turvey.Clive.002

‌

Hi all,

I have to generate a PWM signal of 15%,40KHz  with a short pulse in response with a input.

the task is, at initial the input state will be low. when input will become high then for 450us to 500us the output of should be high and then output switch to PWM signal of 15%,40Khz. and continue till input is high. As input becomes low the output should become low.

I have done it and it's running ok.

I have configure the input signal in interrupt mode for rising and falling edge both. and configured TIM3 Registers (PSC, ARR, CCR) for pwm 15%@ 40KHz.

The timer will continue run but I have put TIM3_CH1 at forced low mode at initial so output will low. when input will become high it will generate a interrupt and in ISR it will put TIM3_CH1 to Forced high mode  so output will high. and it will return from ISR to main function and will check for CC1IF bit state and count up to 20 (i.e. it will check for 20 pulses of 40Khz = 20*25us = 500 us). and when count will reach to >=20 it will put TIM3_CH1 to PWM Mode-1. and now pulses of 40KHz will start. and it works Ok. times of first pulse varies from 450us to 500 us but OK.

The input can be of UPTO 1200Hz freq.

My problem is that what I have done here is for 1 I/O set.

like this I have 5 I/O sets. each have to work like above. 4 Output  will share TIM3 (TIM3_CH1, TIM3_CH2....) and fifth channel will use different Timer.

I can do this same for these 5 I/O sets. but because of it check for CCxIF bit in main function in polling mode and count for 20 pulses to go. it creates problem in timing of first pulse if any interrupt comes. (it is ok from 450us to 500us but not out of it) .

Can DMA help here, can DMA perform this task that it checks 20 times of CCxIF bit and then generate a interrupt, actually I have never worked on DMA so don't know about it or any other suggestion.

You can find my code in attachment for 1 I/O set.

null

[waclawek.jan]

Posted on May 03, 2018 at 22:58

I'd do everything in the timer update interrupt. I even wouldn't set up the EXTI interrupt - even if short pulses have to be catched, it's enough to read the status register of it in that timer interrupt.

However, running an 'F030 at 8MHz this sounds to be an impossible task - that's only 200 machine cycles per 25us timer cycle, and I doubt two channels could be handled in that timeframe, not four, plus the fifth at a different timer, competing for the machine time.

DMA migh help you with one channel but not four or five, the 'F030 simply does not have the resources for that.

I'd reconsider your requirements. Is the low system clock necessary?

JW

[sanju]

Posted on May 04, 2018 at 05:27

I can run the CPU at 48MHz by applying  PLL on internal oscillator. That's will make 1200 machine cycles in 25us time frame.

here is one change I have to use three Timers (TIM3->CH1,CH2 , TIM15->CH1,CH2, TIM17->CH1) for PWM

so you wants to say that I should configure TIM3 , TIM15 and TIM17 for 40KHz signal.

and put only TIM3 to generate interrupt at every update.

then I have to check each of five input pin status PORTx->IDR In this ISR one by one and perform their corresponding action for each. This should be complete in less than 1200 cycles for all 5 inputs.

am I right?

[waclawek.jan]

Posted on May 04, 2018 at 07:36

I would handle each channel in its respective timers' interrupt.

JW

[sanju]

Posted on May 04, 2018 at 07:53

I will configure each timer registers first then will enable each timer's counter in continuous instructions.

So that they will update almost parallel with only delay of  2 or 3 machine cycles.

So I want to use only one timer ISR say tim3.

And I will not do anything in main function.

The complete action (checking for input, taking corresponding action) for each all five inputs will be done in this ISR.

Is there any benefit of using interrupt for all three timers and doing action in their respective ISR.

[waclawek.jan]

Posted on May 04, 2018 at 08:02

You are probably right that it's better to use one single ISR in this case.

Separate ISRs certainly have the drawback of spending precious cycle times on the ISR entry and exit, that's one more point towards using a single ISR.

They may be marginal issues e.g. if you update TIMy registers from TIMx ISR which runs slightly ahead of TIMy, then some values may get updated before TIMy update and some after it. In your particular applications it appears this wouldn't make a difference.

JW

[sanju]

Posted on May 04, 2018 at 08:16

Yes in my application it will not make any noise. 

Even I will not update timer's register (PSC, ARR, CCR) I will just change TIM_CHx mode between forced low, forced high, pwm mode1.

Here I will get one issue that suppose input come at time t1 and that time counter value is 0. Means counter will update after 25us and will interrupt then I will be able to take action for that input.

Means here is a delay between input and output. And delay will slightly larger for 5th input as it will be last in isr. 

Means I have to check input status in main function.

Am I right?

Sorry for bothering you.

[waclawek.jan]

Posted on May 06, 2018 at 11:16

There are many ways to design a system.

Checking input in main would work only if there is nothing else in main which would interfere.Also this would make the initial pulse's length to vary slightly.

You could also still have the EXTI interrupts.

It's upon you to decide, which parameter is of more importance.

JW