I am trying to use DAC Channel 1 on STM32H7 with DMA to control the ramp-up of a PA. The DAC must always be driven (enabled). A ramp-up sequence is written at the start of a burst and a ramp-down at the end of the burst.
The FIFO error flag is set on the second write (ramp-down) and in this case the DMA does not write even though the channel is not disabled. If I write again after this (3rd time) then it works.
Given my setup described below, what can be causing this, and why is it only for the second write?
Initialisation is as follows:
- Initialise DAC1 in Normal mode, DMA enabled.
- Enable DAC1.
- Configure DMA stream1 to use Direct mode, 32-bit peripheral and memory transfer, writing to DHR12R1.
- Configure TMR6 to trigger at required sampling rate.
When writing new DAC values:
- Load first DAC sample to DHR12R1.
- Set NDTR and MOAR for DMA Stream 1.
- Enable stream.
- Enable TIM6.
When doing the write for the second time, a FIFO error interrupt is generated even before the timer is enabled.
I've read AN4031 but do not think it is relevant where it states that the peripheral must be enabled after enabling DMA since my peripheral must always be enabled to always drive the output.
