Did we discuss STM32 in SO8 yet?

[waclawek.jan]

https://www.st.com/content/st_com/en/products/microcontrollers-microprocessors/stm32-32-bit-arm-cortex-mcus/stm32-mainstream-mcus/stm32g0-series/stm32g0x1/stm32g031j6.html

It's the same trick as in the STM8s in SO8 - several IO pads bonded together onto one pin - but still, it's a nice addition to the portfolio.

JW

[Tesla DeLorean]

At some point one wonders what's actually achievable. UFQFPN seems to have size and usability going for them.

[Uwe Bonnes]

The G0/4 datasheet mention "­ Internal 16 MHz RC with PLL option (±1 %)" versus other "Internal 16 MHz factory-trimmed RC (±1%)" . However the reference manuals do not mention any PLL control on HSI16. Has anybody more insight?

[waclawek.jan]

Sounds like a product of some marketing mind. IMO it reads as "HSI can be source to PLL".

Btw. the G0 were supposed to be the next generation F0, but they somehow miss the price point.

JW

[waclawek.jan]

Sure, the SO8 is a gadget. But gadgets can be useful at times.

JW

[Tesla DeLorean]

>>several IO pads bonded together onto one pin

Basically solving with bond wire what could have been achieved with better foresight on the AF pin mux planning side.

A data logger would probably want to escape SD/MMC on a package with less than 64-pins

[Tesla DeLorean]

Lasts two small widgets from here used 28 and 32 lead UFQFPN, physical size, including pin escape being the strongest driver. Wafer scale being a bridge too far for manufacturability. And debug and test being strong secondaries.

Of the low pin count offerings to date, the inability to escape a UART or two being significant frustrations.

[waclawek.jan]

Officially announced yesterday https://www.st.com/content/st_com/en/about/media-center/press-item.html/n4188.html

JW

[Ozone]

I experienced some demand for such small "gadget" MCUs. In the end, it were usually MC PICs or Atmels.

I see it almost entirely aimed at the 8-bit replacement market (which is a mass market), where price trumps everything.