Dear sir, dear missis,
I'm working with an STM32L053r8 on a step by step know-how. My interface with the bootloader runs fine, and I am able to cover the main features provided through this interface. The issues I try to cover now is the right understanding , how the Cortex M0+ runs at assembly level. I done several tests without results today, I can continue to test with an iterative methodology; I can also use the debug port (SWD pin).
I developped an interface to do that, but at this time I didn't received any answer from the debug port. This one is built following Cortex architecture protocole (IHI0031G Debug interface architecture V5.2 architecture specification).
The only thing I can say, to define an hardware protocol at this level is a very important effort, and therefore I missed may be, some details. Or in short my best efforts, were insufficient to translate by hardware, this design document. What seems unclear to me is the specifications at the hardware level, my interface is supposed to work with V5.1 design, and I don't receive any debug interface ID, when I send the 0x85 command ( or 0xA5 command after parity checking) ?
This this surly bit & byte cooking, and maybe have you a more in depth debug port hardware specifications?
Many thanks for support you could provide; hoping this question isn't to deeply hardware?
Best regards.
Butterfly.
