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Dear all, What is the meaning of CNT_INIT in the Figure 120 of Reference manual RM0008 of showing the Internal clock source mode of STM32F103? The tile of this figure is 'Control circuit in normal mode', is it right? Thanks.

DChen.7
Associate II
1 ACCEPTED SOLUTION

Accepted Solutions

@DC.18hen​  you are welcome :)

This bit is set by the UG flag.

You can more check the RM0008, in the timer section that you are using.

For example for (TIM2 to TIM5) section:

"Update: counter overflow/underflow, counter initialization (by software or internal/external trigger)."

The update event can be generated at each counter overflow and at each counter underflow or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller) also generates an update event. In this case, the counter restarts counting from 0, as well as the counter of the prescaler.

0693W00000AM5hyQAD.jpgPlease mark my answer as best by clicking on the "Select as Best" button if it helped :smiling_face_with_smiling_eyes:.

Imen

When your question is answered, please close this topic by clicking "Accept as Solution".
Thanks
Imen

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6 REPLIES 6
Imen.D
ST Employee

Hello @DC.18hen​ and welcome to the STM32 Community =)

CNT_INIT is an internal signal.

I will ask our team to add a description for the CNT_INIT bit.

Please mark my answer as best by clicking on the "Select as Best" button if it helped :smiling_face_with_smiling_eyes:.

Imen

When your question is answered, please close this topic by clicking "Accept as Solution".
Thanks
Imen
DChen.7
Associate II

Hello @Imen DAHMEN​ 

Thank you for your help. And where is the CNT_INIT bit? What is its completely English words stands for?

Best regards,

Dchen

CNT_INIT means counter initialize. and when this bit is set, the counter clock is reset.

Imen

When your question is answered, please close this topic by clicking "Accept as Solution".
Thanks
Imen
DChen.7
Associate II

Thanks Imen.

And is this bit set by user or the UG flag?

Sorry for having so many questions.

DChen

@DC.18hen​  you are welcome :)

This bit is set by the UG flag.

You can more check the RM0008, in the timer section that you are using.

For example for (TIM2 to TIM5) section:

"Update: counter overflow/underflow, counter initialization (by software or internal/external trigger)."

The update event can be generated at each counter overflow and at each counter underflow or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller) also generates an update event. In this case, the counter restarts counting from 0, as well as the counter of the prescaler.

0693W00000AM5hyQAD.jpgPlease mark my answer as best by clicking on the "Select as Best" button if it helped :smiling_face_with_smiling_eyes:.

Imen

When your question is answered, please close this topic by clicking "Accept as Solution".
Thanks
Imen
DChen.7
Associate II

Thank you Imen. I got it from your answer.

DChen