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Could someone confirm (or add to) my understanding of the ADC_CCR_DDS bit in the ADC->CCR register please?


After some experimentation with using the timer trigger with an ADC multichannel scan going to DMA I've found that I can only get most configuration working by setting the DDS bit. The Ref Manual has the following description of this bit:

DMA Disable Selection (for multi-ADC mode)

This bit is set and cleared by software.

0: No new DMA request is issued after the last transfer (as configured in the DMA controller). DMA bits are not cleared by hardware, however they must have been cleared and set

Page 428 of RM0090

My understanding and experience therefore is that: with this bit clear, the DMA will not repeat (even though the ADC is retriggering) without software intervention (i.e. resetting / restarting the DMA). However with this bit set, the DMA always repeats and therefore continuously updates the DMA variable from the ADC peripheral.

So, is the main reason to have the DDS bit cleared if you only want to do a single DMA transfer on incoming data? Can anyone give an example use case please?

Also, searches on the forum suggest that setting the DDS bit can mean you lose data? I assume this is if you don't deal with your data before the next DMA comes in?


Device STM32F43

Not using HAL, but using CMSIS.