2011-04-17 08:05 AM
Cortex M3 Hardfault exception
2011-05-17 05:31 AM
The value in LR at the Hard Fault handler is a magic value which imparts information to the processor about how to return the the prior system/user state. It will not be the faulting instruction.
Implement a REAL Hard Fault Handler to decode the system state and faulting PC. Joseph Yiu has posted several real good examples of this, and his books on the Cortex-M3 is recommended.2011-05-17 05:31 AM
Hi
clive1's suggestion is the way to go. Have a look at the post below - it will give you more info on what he was talking about in his previous post.
[DEAD LINK /public/STe2ecommunities/mcu/Lists/ARM%20CortexM3%20STM32/Flat.aspx?RootFolder=/public/STe2ecommunities/mcu/Lists/ARM CortexM3 STM32/HardFault Exception Why oh why!¤tviews=3001]https://my.st.com/public/STe2ecommunities/mcu/Lists/ARM%20CortexM3%20STM32/Flat.aspx?RootFolder=%2Fpublic%2FSTe2ecommunities%2Fmcu%2FLists%2FARM%20CortexM3%20STM32%2FHardFault%20Exception%20Why%20oh%20why%21¤tviews=3001
Cheers,
Gawie
2011-05-17 05:31 AM
thanx.
I had attached a .bmp file indicating the stack contents at the time of hardfault. Can we interpret it offline(not thro program)?2011-05-17 05:31 AM
Can we interpret it offline(not thro program)?
If you refer to the materials cited, you could interpret it yourself. To do it properly you need to interact with the debugger to review the faulting code, and the register context with respect to that code and what it was doing. Go look at the Thumb2 code you have at around 0x080066CF (the instruction immediately before) You can't review the core's register from a BMP
2011-05-17 05:31 AM
This is also a good overview of how to decode the hardfault stack info:
http://www.keil.com/appnotes/files/apnt209.pdf
http://www.keil.com/appnotes/files/apnt209.pdf
And I think there was a typo, the bitmap suggests the fault should be just before address 0x08006CCF.Andrew
2011-05-17 05:31 AM
Yes 0x08006CCF, my transcription error