2024-12-14 11:33 PM
Dear All,
I am working for the first time with a production set of code and I am asking some help in the following question/ uncertainty ,
The STM32F103Cx device has a phew Core exception IRQ's as shown below
/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
The company I am doing this work for use baremetal coding so my question is do I enable these IRQ's the same way and do a IRO handler in the same way as I would for an Timer IRQ for example ,
as such
//3.TIM2 interrupt Init Vectors and enable it */
NVIC_SetPriority(TIM2_IRQn,1);
NVIC_EnableIRQ(TIM2_IRQn);
// The handler
void TIM2_IRQHandler(void)
{
TIM2_IntFlagClear();// Clear Int Flag TIM2
// handler code here
}
Which are the most important exceptions to handle ?
I appreciate any help or hints as I am confused and uncertain at the moment
Best Reagrds
Pje
2024-12-15 06:36 AM
These interrupts don't require a call to NVIC_EnableIRQ to be enabled, they are enabled by default, though some require additional configuration in order to fire like SysTick.
> Which are the most important exceptions to handle ?
The ones most relevant to your program. Out of the list you mention, SysTick is typically handled, though it's not required. The others are handled but go into an infinite error loop. If they are triggering, you should work to debug and fix your program rather than worry about handling them.
Generally you should handle error-type interrupts the same way as a HardFault--go into some piece of safe code where you can read out registers and debug your code.
2024-12-15 06:40 AM
Perhaps pull a copy of the ARM TRM for the Cortex-M3, or ST's Programming Manual.
See also Joseph Yiu's books
The System Handlers are enabled and controlled via processor configuration registers or MPU settings, etc
Most critical would be Hard Fault Handler, and SysTick
2024-12-16 06:46 AM
Hi All,
Thank you for the valuable comments,I appreciate it,
I will pull the document as advised and look for the book,
I think I get what you are saying that when these exceptions occur I need to look for the reaosns and that is most properly a bad peace of code causing the exception ,with that said I will need to read and try to understand and possibly ask help again
Thanks a million
Pje