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Configuring System Clock with only Device Peripheral Access Layer on Nuceo L476RG

MKrue
Associate

‎2019-08-11 06:22 PM

Hey, so after taking a 10 month break from embedded software development I decided i want to go as baremetal as reasonable.

While previously having worked with CubeMX generated projects i always found myself directly addressing registers anyways.

What really evades me is clock configuration, the gritty details of picking prescalers etc.

I dug up a NUCLEO L476RG and would like to set up the System Clock at maximum possible frequency using the HSE oscillator, but i am pretty lost at how to determine the various prescalers with the whole flash latency wait states etc.

I spent the last few hours on google searching for stuff but nobody really explains in detail why they did what they did.

If someone could provide some details on what to look for in the datasheet and reference manual, provide some sample code and the likes i'd be grateful

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Bill Dempsey
Senior

‎2019-08-11 08:43 PM

My free advice is to study the setup by using CubeMX. Change the view to the clock setup page and all the detail from a block-diagram perspective will be shown. You can tweak the HSE input and have CubeMX solve for a solution that meets your system clock needs. The HAL code distributed by ST follows along very well.

The reference manual for the specific processor will have the guidance on *how* to set up the registers; the datasheet will show *what* the values can be.

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waclawek.jan
Guru

‎2019-08-12 01:51 AM

The procedure basically is:

  • enable required clocks in RCC (e.g. for PWR, FLASH - the latter may be by default OK, check)
  • configure PWR_CR1.VOS range for the given frequency (it may be by default OK, check)
  • set FLASH latency as required, see Read access latency subchapter in RM
  • set APB prescalers so that their maximum operating frequency is not violated, see General operating conditions in DS. In 'L476 it's not an issue as both APBs can go up to 80MHz as well as AHB
  • enable HSE, wait until ready
  • set the required PLL source and PLL parameters, enable PLL, wait until ready
  • switch system clock to PLL, wait until ready

JW

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