Comprehension on DMA(concurrent stream, FIFO, burst mode,double buffer)

[cyqdtc]

Posted on June 05, 2014 at 12:07

The DMA for stm32F4 series has some advanced functions, could I ask for clarification here?

• Concurrent stream: Can two streams transmit data at the same time? Since one byte transfer is allowed. If the bus width is 32bit, 4 concurrent transmission is possible. Btw, what is the width of the AHB bus for STM32?

• FIFO mode: If concurrent transmission is not possible, I guess FIFO could be used here. FIFO would help to wait data ready from low speed peripherals to DMA without occupying the AHB bus. When a certain amount of data are ready, the chunk of data will be sent to memory together. Is my understanding correct?

Four-word depth 32 first-in, first-out memory buffers (FIFOs) per stream

What does that mean? How many data can be stored in the FIFO? 4 or 4*32?

• Burst mode: What does actually burst mode do? It says in datasheet that 65535 data can be transmitted. What is the relation between 65535 with the burst mode?

• Double buffer mode:

Double-buffer type transactions: double buffer transfers using two

memory pointers for the memory (while the DMA is reading/writingfrom/to a buffer, the application can write/read to/from the otherbuffer). -----From reference manual of STM32F4

My question is: During the DMA transmission, the AHB bus is not available for Cortex M4, how could the application read from the other buffer?

#dma

[waclawek.jan]

Posted on June 05, 2014 at 12:24

> Concurrent stream: Can two streams transmit data at the same time?

No. > Since one byte transfer is allowed. If the bus width is 32bit, 4 concurrent transmission is possible. No. Byte transfers are performed one byte at a time, with control lines indicating, which bytes are valid. > Btw, what is the width of the AHB bus for STM32? 32 bit. > FIFO mode: If concurrent transmission is not possible, I guess FIFO could be used here. > FIFO would help to wait data ready from low speed peripherals to DMA without occupying > the AHB bus. When a certain amount of data are ready, the chunk of data will be sent to > memory together. Is my understanding correct? Yes. > Four-word depth 32 first-in, first-out memory buffers (FIFOs) per stream

> What does that mean? How many data can be stored in the FIFO? 4 or 4*32?

4x32 bits, i.e. 4x4=16 bytes. > Burst mode: What does actually burst mode do? Allows the DMA to use bursts on the AHB bus. It occupies the bus for the programmed number of beats. > It says in datasheet that 65535 data can be transmitted. What is the relation between 65535 with the burst mode? None. 65535 is simply the maximum number of DMA transfers. During that, if the FIFO gets reasonably full, and DMA is configured for bursts, it transfers using burst. > My question is: During the DMA transmission, the AHB bus is not available for Cortex M4, how could the application read from the other buffer? The bus is not available for the CPU only while DMA performs the transfer to memory, i.e. if there are no bursts, DMA holds up the AHB bus only for one AHB clock (plus one cycle for arbitration to return to CPU, if applicable), if bursts, DMA holds up the AHB for the programmed number of beats. Then it releases the AHB bus until its FIFO gets reasonably full again. Read AN4031. JW

[stm322399]

Posted on June 05, 2014 at 14:46

I am pretty sure that DMA1 and DMA2 can do concurrent accesses if they target different slaves, thanks to the interconnect matrix.

As far as I understand, an F427 can do simultaneously: * CPU access to Flash (reading code) * DMA1 access to SRAM (to transfer some buffer) * DMA2 access to SDRAM (another buffer) Of course when you try to understand that sort of intricacy, make sure you have the errata sheet of the MCU close to you !

[waclawek.jan]

Posted on June 05, 2014 at 15:16

Okay, so let me rephrase:

- two streams of *the same DMA unit* don't transfer simultaneously on any bus. They even don't act simulatenously at all - once DMA starts a transaction in one of its streams, it does not interrupt it and go for other stream until it finishes this transaction. See AN4031, ch3. - two matrix masters (e.g. two different DMA units) don't transfer simultaneously on the same slave bus, even if they would want to transfer a less-than-buswidth data JW

[cyqdtc]

Posted on June 06, 2014 at 04:18

Really appreciate your explanation. Very clear. Also thank you for mentioning AN4031

rh

[cyqdtc]

Posted on June 06, 2014 at 04:19

Thanks for the comments�