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Clock configuration for stmf411 series mcu

teja457257
Associate
Posted on March 28, 2016 at 15:21

Hi STM,

As part of our project we are using STM32F411RET6 series MCU, We have followed clock configuration from the below link

http://www.st.com/web/en/catalog/tools/PF257927

As Maximum clock for the MCU what we are using is 100Mhz.

And our requirement is

*    mcu has run at 100Mhz or (Maximum clock)

*    We are using SPI peripheral and TIM7 in which both are using APB1 clock .

below are clock configuration we are using and we have on board external 26Mhz  crystal oscillator

cpu_clock                 : 100000000

HSE_SOURCE                : RCC_HSE_ON

AHB clock divder          : RCC_SYSCLK_Div1

APB1 clock divder         : RCC_HCLK_Div4

APB2 clock divder         : RCC_HCLK_Div2

Pll source                   : RCC_PLLSource_HSE

PLLM                       : 13

PLLN                       : 200

PLLP                       : 4

PLLQ                       : 9

System clock source       : PLL clock

systick clock source      : SysTick_CLKSource_HCLK

Internal flash wait state : 3 cycles

Below is my Brief understanding about the configuration

cpu clock is at 100 Mhz

AHB clock at 100 Mhz

APB1 clock at 100/4 = 25 Mhz

APB2 clock at 100/2 = 50 Mhz

Please let me know my understanding is right.

Now Question is, from clock configuration tool if Cpu clock is running at 100 Mhz( possible max speed ) max APB1 clock is 36Mhz from above configuration APB1 is 25Mhz, which is impacting throughtput of SPI periphral what we are using. And at the same time we are using TIM7 for internal monitoring purpose. Is there any way to bump up the APB1 clocks so that it can run at its maximum speed(36Mhz).

From clock configuration tool if cpu_clock is 72Mhz then APB1 is running at is maximum speed i.e., 36Mhz, but we dont want cpu clock to run at lower speed.

Please provide us a solution which unblocks us.

Please let me know if any more data needed.

Thanks & Regards,

Teja.

#clock-configuration
1 REPLY 1
Posted on March 28, 2016 at 17:32

Data sheet shows APB1 capable of 50 MHz operation. (Fig 3, Pg 15)

http://www.st.com/st-web-ui/static/active/en/resource/technical/document/datasheet/DM00115249.pdf

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