Clarifications about STM32H7 interrupts group priorities and subpriorities

[Gpeti]

The notion of group priority and subpriority is not very clear in the STM32H7 programming manual.

First the manual states that:

According to the value of the register AIRCR (0xFA050000) the splitting between group priority and subpriority for interrupts should be:

But then in the NVIC description I read:

What is "n" ? At first I thought that  it was the number of "xxx" in table 56 but I noticed that I could only write the 4 least significant bits in IPR registers , which means n=4 ?

How to set group and subpriority priorities if only 4 bits can be written in IPR registers ?

[STea · Accepted solution]

Hello @Gpeti ,

here are some clarifications about interrupt prioritization :

• Each interrupt source has an 8-bit interrupt priority value
• The  8 bits are divided into pre-empting group priority levels and non-preempting “sub-priority” levels
• Sub-priority levels only have an effect if the pre-empting group priority levels are the same
• The software programmable PRIGROUP register field of the NVIC chooses how many of the 8 bits are used for “group priority” and how many are used for “sub-priority”
• Group priority is the Pre-empting priority
• Lower numbers are higher priority
• Hardware interrupt number is lowest level of prioritization
• E.g: IRQ3 is higher priority than IRQ4 if the priority registers are programmed the same

ST micro-controllers implements 4 bits (MSB) from the 8 bits reserved for priority so only the marked region in the screen below (bits marked in green in the red rectangle) is valid  for STM32.

BR

[Gpeti]

Thank you, I was missing this table. Would be nice to put it in the reference manual or programming manual

It's a bit weird that the default value of PRIGROUP in AIRCR is not a valid value (even if I understood that it works fine with the 4 bits being the group priority)

Regards

[ShawnP]

"ST micro-controllers implements 4 bits (MSB) from the 8 bits reserved for priority so only the marked region in the screen below (bits marked in green in the red rectangle) is valid  for STM32."

I spent quite a bit of time looking across all the available documentation I could find for the details you presented here.

Where specifically could I have looked to find these details?

The referance manual I was using does not include this (STM32 Cortex®-M33 MCUs programming manual) information.

What confused me was I have sample code (provided by ST as part of STM32CubeIDE) that has the following definitions that seem in direct conflict with the information referenced above:

#define NVIC_PRIORITYGROUP_0         ((uint32_t)0x00000007) /*!< 0 bit  for pre-emption priority,
                                                                 4 bits for subpriority */
#define NVIC_PRIORITYGROUP_1         ((uint32_t)0x00000006) /*!< 1 bit  for pre-emption priority,
                                                                 3 bits for subpriority */
#define NVIC_PRIORITYGROUP_2         ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority,
                                                                 2 bits for subpriority */
#define NVIC_PRIORITYGROUP_3         ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority,
                                                                 1 bit  for subpriority */
#define NVIC_PRIORITYGROUP_4         ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority,
                                                                 0 bit  for subpriority */

 programming manual contains (this information - split across pages BTW):

I admit I'm not an expert on the STM32 platform but I'm not a total noobie either.   I found this very confusing and I still don't know where I can go to get definitive documentation on how this work for STm32 devices since the programming model in the documention does not seem to be what's really implemented in the devices and the reference manual has nothing on it either (RM0456).

Any help would be appreciated.

Shawn

[Pavel A.]

> Where specifically could I have looked to find these details?

In the PM (Programming manual). The NVIC and above mentioned interrupt details belong to the ARM core of STM32 MCUs. ARM provides "template" programming manuals that Cortex-M implementers can adapt for their products. That is basically the STM32 Programming manual. For more details  you can look in the ARM documentation on their site (but I won't recommend it - there it is full of esoteric details and info not relevant to STM32s). Better get a book about Cortex-M, such as Joseph Yiu.

So again: the interrupts and NVIC of STM32s are plain Cortex-M, except of two details that implementor can choose:

1. Number of priority bits - as described above by @STea 

2. Number of custom IRQ vectors (above the 16 standard vectors): this defines the total size of the vectors table and therefore its alignment. This number is in the data sheet (DS) document and in the model specific .h files.

[ShawnP]

Thanks for the additional information.   I was able to find the specific number of priority levels (number of bits) in the data sheet and reference manual for the stm32u575 but no specific guidance in the programmin manual on how to configure those bits when they are a reduced subset for a specific part.  @STea documents this above but I find no place in the "official" documentation where this is made clear - but there's a lot of pages in these documents so perhaps I missed it 😉