Clarifications about STM32H7 interrupts group priorities and subpriorities

[Gpeti]

The notion of group priority and subpriority is not very clear in the STM32H7 programming manual.

First the manual states that:

According to the value of the register AIRCR (0xFA050000) the splitting between group priority and subpriority for interrupts should be:

But then in the NVIC description I read:

What is "n" ? At first I thought that  it was the number of "xxx" in table 56 but I noticed that I could only write the 4 least significant bits in IPR registers , which means n=4 ?

How to set group and subpriority priorities if only 4 bits can be written in IPR registers ?

[STea · Accepted solution]

Hello @Gpeti ,

here are some clarifications about interrupt prioritization :

• Each interrupt source has an 8-bit interrupt priority value
• The  8 bits are divided into pre-empting group priority levels and non-preempting “sub-priority” levels
• Sub-priority levels only have an effect if the pre-empting group priority levels are the same
• The software programmable PRIGROUP register field of the NVIC chooses how many of the 8 bits are used for “group priority” and how many are used for “sub-priority”
• Group priority is the Pre-empting priority
• Lower numbers are higher priority
• Hardware interrupt number is lowest level of prioritization
• E.g: IRQ3 is higher priority than IRQ4 if the priority registers are programmed the same

ST micro-controllers implements 4 bits (MSB) from the 8 bits reserved for priority so only the marked region in the screen below (bits marked in green in the red rectangle) is valid  for STM32.

BR

[Gpeti]

Thank you, I was missing this table. Would be nice to put it in the reference manual or programming manual

It's a bit weird that the default value of PRIGROUP in AIRCR is not a valid value (even if I understood that it works fine with the 4 bits being the group priority)

Regards