Center aligned pwm and DMA

[DDona.1]

How the hell it makes sense to have 2 UEVs per period in center aligned PWM mode and not be able to choose which one generates request for DMA and update of registers. For an interrupt it's possible to choose if underflow or overflow events generate it with CR1_CMS bits.

Is the timer really so flawed in center aligned mode or do I miss something?

This question is about STM32L4 but I am quite sure on all STM32 series, timers are the same.

[waclawek.jan]

Is this just a rant, or is there also a question?

I never understood the gist of up-down mode as such, but why don't you simply accept the status quo, and provide values for DMA for both Update events?

> For an interrupt it's possible to choose if underflow or overflow events generate it with CR1_CMS bits.

Not for the Update interrupt, apparently, just the CCx interrupts. And, I believe, the CCx-triggered DMA work in the same way, so you may want to resort to those perhaps, instead of Update triggered DMA.

JW

[DDona.1]

That was just some frustration with a hope to get a hint.

Doubling DMA transfers was my last resort as burst DMA transfer speed is 2MHz already.

By the way correct solution is to use repetition counter. I am not sure how to sync on underflow or overflow, as datasheet (or some other ref. document) says that overflow or underflow update is synced depending if rep. counter was updated before or after timer's launch, but after a quick test that doesn't seem to change anything.

[waclawek.jan]

How is using repetition counter more correct than using CCx as trigger? (It may be, this is not a provocation but a question).

> I am not sure how to sync on underflow or overflow

Which one of them will occur as the first after enabling timer, is given by the state of DIR bit (and perhaps also CNT) at the moment of enabling the timer.

JW