Capacitance of OSC_32 pins

[Panda]

Hello,

Datasheet DS14791 Rev 4 has a note on page 161 stating that PCB and pin capacitance for the OSC_IN/OSC_OUT Interface can be assumed as 4 pF combined.

I qoute: "For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors,
designed for high-frequency applications, and selected to match the requirements of the
crystal or resonator (see Figure 20). CL1 and CL2 are usually the same size. The crystal
manufacturer typically specifies a load capacitance, which is the series combination of CL1
and CL2. The PCB and pin capacitance must be included (4 pF can be used as a rough
estimate of the combined pin and board capacitance)."

I would calculate C1 = C2 = 2*(C_LOAD - C_STRAY) and assume C_STRAY with 2 pF in this case.

- Can you confirm that this is the correct way to size C1 and C2?

I was wondering if the same assumption can be made for OSC32_IN and OSC32_OUT Pins. I didn't find a note on that. Otherwise I would go by the chapter 5.3.17 I/O port characteristics and assume 5 pF per pin.

- But since this a quite big difference to the 4pF combined from the note I assume that a similar assumption can be made for OSC32?

Best Regards

Lucas

[mƎALLEm · Accepted solution]

Hello,

I invite you to read this article: "How to select a compatible crystal and load capacitors for STM32 with layout guidelines" especially the section 4. Calculation of the external load capacitors value:

"Note that in most of STM32 datasheets, C_IO is provided as 5 pF and this is the worst case typical condition of 5 pF which is generic to all I/Os."

And the estimation of Cs is around 3pF.

Refer also to these posts:

What is the actual STM32 pin capacitance (for the purpose of sizing an HSE crystal)?

Crystals and load capacitors for stm32l432

Hope that helps

[Panda]

Ah yes, thank you.

This was very helpful!