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How to select a compatible crystal and load capacitors for STM32 with layout guidelines

mƎALLEm
ST Employee

Introduction

As with many microcontrollers, STM32 MCUs could be clocked by an external source like crystals (XTAL) or crystal oscillators (XO). This is in addition to internal clocks such as LSI, HSI, MSI, CSI etc. For crystals, a preliminary calculation is needed to determine if it is suitable for a specific STM32 MCU.

This article is intended for new STM32 users. It shows by examples how to know if the crystal is suitable for your STM32 or not.

And finally, an important point: The best selection of components is only worth half as much if the corresponding layout does not fit. Therefore, we recommend reading section 5 regarding the layout.

1. HSE and LSE structures

The HSE and LSE blocks of STM32 MCUs are based on a Pierce oscillator:

Figure 1. Pierce oscillator structureFigure 1. Pierce oscillator structure

 

 

 

Where:

  • Inv: the internal inverter that works as an amplifier.
  • Q: crystal quartz or a ceramic resonator.
  • RF: internal feedback resistor.
  • RExt: external resistor to limit the inverter output current and to form a lag network with CL2 to add additional phase shift for frequencies of 8 MHz or below.

  • CL1 and CL2: are the two external load capacitances. Generally, they have the same value.
  • Cs: stray capacitance, sum of the device pin (OSC_IN and OSC_OUT) and the PCB (a parasitic) capacitances. It is the equivalent parallel capacitance seen by the crystal.

The Pierce Oscillator (was a US patent 2'133'642, filed in 1924, expired in 1955) is known for its stable oscillation in conjunction with a quartz crystal. This is why it is by far the most commonly used gate oscillator today. If you want to learn more about how a Pierce Oscillator works, we recommend reading, AN2867, section 3, or this article by Ramon Cerda.

To start the oscillator, it requires a certain minimum amount of energy. The next sections show how to make some calculation to define if a crystal is suitable for your STM32 (HSE or LSE).

2. Calculation to validate the crystal compatibility with STM32

To ensure the minimum of energy to let the oscillator start and sustain the oscillation, it needs to meet this condition:mALLEm_0-1741348529814.png

or

mALLEm_1-1741348562504.png

Some product datasheets specify gm min while others Gmcritmax.

Where: 

  1. gm min = 5 * Gmcritmax

    gm is the oscillator transconductance of the product. Each STM32 product has a specific value provided in its datasheet. It is also provided in the AN2867 as gm min or Gmcritmax


    For HSE:

    Figure 2. HSE transductance by productFigure 2. HSE transductance by product

    Figure 2. HSE transconductance by product

     

     


    For LSE:

    Figure 3. LSE transductance by productFigure 3. LSE transductance by product

    Figure 3. LSE transconductance by product


     

  2. gm crit:

mALLEm_6-1741349154048.pngWhere:

  • ESR: the crystal equivalent series resistance provided in its datasheet. 
  • F: the crystal nominal oscillation frequency.
  • C0: the crystal shunt capacitance provided in its datasheet.
  • CL: the crystal nominal load capacitance provided in its datasheet.

Note that the figures 2 and 3 were extracted from the AN2867 rev 23. The application note is in a continuous update each time a new STM32 MCU is released. So, please refer to that application note if you do not find your STM32 MCU in these tables.

3. Calculation examples

In this section, we focus on the HSE crystal calculation.
The crystal gain margin for LSE is calculated in the same manner but with considering the selected drive level.

3.1 Example of suitable crystal found after calculation

Let us take the crystal part number CX3225GA8000D0PTVCC (datasheet attached) with STM32H743 HSE.

This is the crystal specification from its datasheet:

Figure 4. A screenshot from CX3225GA8000D0PTVCC crystal datasheetFigure 4. A screenshot from CX3225GA8000D0PTVCC crystal datasheet

 

 

 

And this is the STM32H743 HSE specification from its datasheet:

Figure 5. A screenshot from STM32H743 datasheet showing Gmcritmax valueFigure 5. A screenshot from STM32H743 datasheet showing Gmcritmax value

 

 

 

mALLEm_7-1741349360791.png

 

mALLEm_8-1741349420721.pngThis crystal is suitable for STM32H743 MCU.

3.2 Example of an incompatible crystal after calculation

Now, let us take the crystal part number LFXTAL081620 (datasheet attached at the end of the article) for the same MCU STM32H743 HSE.

Figure 6. A screenshot from LFXTAL081620 crystal datasheetFigure 6. A screenshot from LFXTAL081620 crystal datasheet

 

 

 

mALLEm_10-1741349618519.png

mALLEm_11-1741349627874.png

This crystal is incompatible with the STM32H743 MCU.

Tip: According to the gain margin formula, it is better to select a lower rated frequency for the crystal to reduce the value gm crit as much as possible, thereby increasing the gain margin.

Attached at the end of the article, you will find an STM32 Crystal Calculator.xlsx file that can help you to calculate the gain margin and quickly find a suitable crystal.

4. Calculation of the external load capacitors value

After finding the suitable crystal, it is time to calculate the external load capacitors value of CL1 and CL2. The formula is as the following: mALLEm_12-1741349792086.png

In general, these two capacitors (CL1 and CL2) are selected with the same capacitance: CL1 = CL2, which results in:

mALLEm_0-1743153284389.png

After transforming the equation, the result is:

mALLEm_1-1743153327007.png

Cs (stray capacitance) is an estimation of the sum of the MCU pins and the parasitic capacitance of the PCB. Experience has shown that the value is between 2...3 pF.

Note that in most of STM32 datasheets, CIO is provided as 5 pF and this is the worst case typical condition of 5 pF which is generic to all I/Os.

Where:

  • CIO = pin capacitance
  • CPCB: capacitance of the PCB.
  • Cs = CIO + CPCB  = 3 pF

If we take the example of CX3225GA8000D0PTVCC with STM32H743.

The crystal CL= 8 pF (taken from its datasheet, see figure 4).

So :

  • Cs = 3 pF
  • C= 8 pF

The external load capacitors will have the value:     

mALLEm_2-1743153478920.png

This capacitance value is a standard value of capacitors on the market. To find capacitor standard values, please refer to this link to get the capacitors standard value.

Figure 7. Standard capacitor value in this case is 10 pFFigure 7. Standard capacitor value in this case is 10 pF

Please note that selecting a non-exact value for the calculated capacitor affects the frequency of the oscillator (and therefore the pullability of the crystal). The more the capacitor value deviates from the calculated value, the greater the frequency deviation from the nominal frequency of the crystal.

Also note that the value of the external load capacitor in the case of LSE can best be determined empirically. Each time the capacitor changes, the RTC output frequency is measured at the MCO with a universal counter until the frequency of 32.768 kHz is reached as accurately as necessary.

Finally, it's interesting to note that one of the ST partners named ECS provides an easy tool on this link. The tool helps you to select a compatible crystal for HSE and LSE for their products based on the ST recommendations.

5. Layout considerations

Despite the best values for the capacitors and the crystal, stable operation over the entire voltage and temperature range can be difficult if a suitable layout has not been developed. It is therefore highly recommended to work through the important notes in AN2867, section 7, in order to achieve the desired result.

The following image shows figure 14 of AN2867 as an example, in which the pins to which the HSE and LSE crystals that are connected, are marked with green, orange and pink circles. For better clarification, the ballout from the datasheet is also shown on the right, in which the relevant pins are marked.

What is important here is the realization of the 'trough'-shaped shielding of both HSE crystal and LSE crystal. Each of the crystals has:

  • its own, light blue GND 'base plate', which is separated from the other GND (white dividing line).
  • An additional red GND 'wall' around the crystal and its load capacitors on its assembly layer with several vias to the respective GND 'base plate' of the crystal.
  • A separate GND connection of its GND 'base plate' to the nearest VSS pin, possibly separate from the other VSS, as shown in AN2867, Figure 15 

an2867 Figure 14 incl Ballout.png

Conclusion

This is a preliminary calculation to confirm that a crystal is or is not suitable for a particular STM32 MCU. Other parameters must also be calculated. It also highlights the importance of a suitable layout. Please refer to the AN2867 «Guidelines for oscillator design on STM8AF/AL/S and STM32 MCUs/MPUs” application note for more details. 

Related links 

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Last update:
‎2025-04-17 1:09 AM
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