This is a weird one 🙂 I'm using the STM32F769 device, and I have the LTDC peripheral running at low speed (8MHz PCLK). When I send a CAN message to the unit, the CAN RX interrupt is invoked, and only when the ISR exits, an LTDC error interrupt is raised, which indicates FIFO underrun. Here is a code snippet below:
void conv_u32_to_buf(uint32_t num, uint8_t buf[])
{
memcpy(buf, (void*)&num, 4);
}
void CAN1_RX0_IRQHandler(void)
{
CAN_TypeDef* can = CAN1;
// If CAN message available in the FIFO
if ((can->RF0R & CAN_RF0R_FMP0) != 0U)
{
uint8_t data[8];
// Get pointer to mailbox
CAN_FIFOMailBox_TypeDef* mailbox = &can->sFIFOMailBox[CAN_FILTER_FIFO0];
// This does not work
uint32_t tmp = mailbox->RDLR;
conv_u32_to_buf(tmp, &data[0]);
tmp = mailbox->RDHR;
conv_u32_to_buf(tmp, &data[4]);
// This works
//tmp = mailbox->RDLR;
//memcpy(&data[0], &tmp, sizeof(uint32_t));
//tmp = mailbox->RDHR;
//memcpy(&data[4], &tmp, sizeof(uint32_t));
// Dequeue the message from the peripheral, as we have wha
can->RF0R |= CAN_RF0R_RFOM0;
}
}
Interesting Note #1: If I do the memcpy directly in the ISR, there is no issue, but if I call conv_u32_to_buf, passing in num by value, it invokes the error
Interesting note #2: If I change conv_u32_to_buf so that pointer to num is passed if, there is no error.
Interesting note #3: the NVIC priorities for LTDC are 0-0 (preemptive, sub-priority), and CAN RX are 0-1
CAN is on a lower sub-priority, and the LTDC does not interrupt it
Interesting note #4: The same code on the STM32F469 does not raise an LTDC error. The M4 platform has worked well for us for 5 years.
So any ideas as to why this is failing on the M7 device? Silicone bug, or perhaps something I'm missing, o are not aware of?
Rob
