2025-10-16 3:39 AM
Hi,
In STM32H56xx, if both EDATA1_EN and EDATA2_EN are set to 0, can I place application code in the high-cycle data flash memory?
I am confused by these two descriptions in the reference manual:
Solved! Go to Solution.
2025-10-17 9:34 AM
Hi @Snaku,
No, this area (high-cycle data flash) will be disabled if EDATA1_EN and EDATA2_EN are set to 0.
In this case, the entire flash memory is used for executable code, accessible at the standard address around 0x0800_0000.
However, if the high-cycle data flash area is enabled (EDATAx_EN = 1), this area is then remapped to a different address range (typically 0x0900_0000), separate from the code area, to prevent the CPU from executing code in the data flash region., let me explain in detail:
By default, the entire flash memory is used to store executable code, accessible at the standard address starting around 0x0800_0000.
This code area features a 9-bit ECC for every 128 bits of data, and each sector is 8 kB in size.
The microcontroller allows configuring a portion of the flash as a high-speed data flash region, dedicated to data storage with high endurance (up to 100,000 erase cycles).
This region is mapped to a different address range, around 0x0900_0000, and uses a different ECC scheme (6 bits for every 16 bits of data) with smaller sectors of 6 kB.
This configuration is enabled via the EDATA1_EN and EDATA2_EN bits in the User Option Bytes, along with the EDATA1_STRT and EDATA2_STRT thresholds that define the start of this region within each bank.
If both EDATA1_EN and EDATA2_EN are set to 0, the high-speed data flash region is not enabled, so the entire flash is available for code in the 0x0800_0000 range.
If you enable the data flash region (EDATAx_EN = 1), part of the flash is reserved for data storage in the 0x0900_0000 range, and you should not place executable code there.
Thank you.
ELABI.1
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2025-10-17 9:34 AM
Hi @Snaku,
No, this area (high-cycle data flash) will be disabled if EDATA1_EN and EDATA2_EN are set to 0.
In this case, the entire flash memory is used for executable code, accessible at the standard address around 0x0800_0000.
However, if the high-cycle data flash area is enabled (EDATAx_EN = 1), this area is then remapped to a different address range (typically 0x0900_0000), separate from the code area, to prevent the CPU from executing code in the data flash region., let me explain in detail:
By default, the entire flash memory is used to store executable code, accessible at the standard address starting around 0x0800_0000.
This code area features a 9-bit ECC for every 128 bits of data, and each sector is 8 kB in size.
The microcontroller allows configuring a portion of the flash as a high-speed data flash region, dedicated to data storage with high endurance (up to 100,000 erase cycles).
This region is mapped to a different address range, around 0x0900_0000, and uses a different ECC scheme (6 bits for every 16 bits of data) with smaller sectors of 6 kB.
This configuration is enabled via the EDATA1_EN and EDATA2_EN bits in the User Option Bytes, along with the EDATA1_STRT and EDATA2_STRT thresholds that define the start of this region within each bank.
If both EDATA1_EN and EDATA2_EN are set to 0, the high-speed data flash region is not enabled, so the entire flash is available for code in the 0x0800_0000 range.
If you enable the data flash region (EDATAx_EN = 1), part of the flash is reserved for data storage in the 0x0900_0000 range, and you should not place executable code there.
Thank you.
ELABI.1
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2025-10-17 9:59 AM
Hi @ELABI.1 for complete info "should not place" or "could not place" or execution is complete prohibited?
I mean 0x09 is normal adress space and code can jump here or ?
2025-10-17 12:35 PM
Hi @Snaku
This post has been escalated to the ST Online Support Team for additional assistance. We'll contact you directly.
Regards,
Billy
2025-10-19 6:50 PM
Hi Billy,
Thanks for your support, from ELABI.1's explanation, my understanding as below.
By default, the entire flash can be used for application code, CPU can execute code from entire flash memory which address is around 0x0800_0000.
After user set EDATAx_EN to 1 and config EDATAx_STRT sector number, some flash memory region with high endurance will be remap to 0x0900_0000, then these memory regions become EDATA memory, CPU can't fetch code from EDATA memory.
So, for example on 2M byte device, by default user can place application code on the sector 120 ~ sector 127 (0x080F_0000 ~ 0x080F_FFFF). But if the user enabled the EDATA memory, 0x080F_0000 ~ 0x080F_FFFF will be remap to 0x0900_0000~0x0900_BFFF, and CPU can't fetch code from this memory area.
please let me know if I miss understanding
Snaku
2025-10-20 2:05 AM
Hi @MM..1 ,
The high-cycle data flash area (starting at 0x0900_0000) is a normal and valid address space, accessible by the CPU for reading and writing data. However, executing code from this area is strictly prohibited. If the CPU attempts to fetch instructions from this area, it will trigger a bus error, thereby preventing any execution.
The only exception is if code is stored there as initialization code, but it must then be copied to SRAM before execution, which is a valid scenario.
Thanks,
ELABI.1
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2025-10-20 2:31 AM
Hi @Snaku,
If your program code into sectors 120-127 and then enable EDATA, the contents of the sectors will appear scrambled, mixed up, and have incorrect ECC. They need to avoid doing this. It's either code or data for sectors 120-127, never both simultaneously.
Thanks,
ELABI.1
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