bus width vs access width

[ranran]

Hello,

We are using FMC interface.

Is it that the access must be in the same size of the memory data bus ?

In software, the bus width is defined as following:

MemoryDataWidth = FMC_NORSRAM_MEM_BUS_WIDTH_16;

and the access is 16 bit as following:

So, is it illegal to make the access in 32-bit if the data width is 16-bit ?

Thank you!

[waclawek.jan · Accepted solution]

> Is it that the access must be in the same size of the memory data bus ?

No.

Read the manual.

FMC chapter, Supported memories and transactions / General transaction rules. You again neglected to tell us that you are using H7, there this sentence applies:

 The AXI transaction size depends on memory region MPU attributes

and in the other thread you started I gave you a link to a thread where that was discussed; read it.

JW

[Tesla DeLorean]

The system decomposes transactions to the right sizes. Burst or sequenced accesses might be optimized, or folded at the FMC level depending on the configuration, or via other peripheral units attached to the FMC.

The processor handles some unaligned accesses, others will fault depending on the core implementation. For example 64-bit LDRD/STRD will fault across most cores for unaligned accesses. As I recall most cores will break a transaction in two, but don't have transistors to go further.