BAUD RATE CALCULATION FOR USART IN STM32

[MMoba.1]

PLEASE EXPLAIN WHY 104.167 IS CONVERTED TO 104.1875 AND HOW ITS ENCODED AS 0X683

MY UNDERSTANDING FOR ENCODING IS 104 IS CONVERTED TO HEX AS MANTISSA PART AS DECIMAL TO HEX AND O.1875 IS CONVERTED SEPARATELY FOR FRACTION PART.

IF I USE FCLK/BAUDRATE I.E 16MHZ/9600= 1666.666d =1667d=0x683h

why use above formula i don't understand.

[TDK]

Because some amount of error is allowed in the USART clock rate, and it's the closest achievable value. Typically under 1% is fine. No clock has perfect accuracy.

104.1875 = 0x683 / 16

[Tesla DeLorean]

The BRR uses a fixed-point representation, ie Q12.4

int((104.1875 * 16) + 0.5) = 1667 = 0x683

Personally I've been using BRR = APBCLK / BAUD for 13+ years, it is simpler to explain/compute.

You are basically computing the 16x rate, the USART divides the window into 16 pieces, and can realign the input based on the center time of the bit, basically they have a 16-bit shift register on the input, and they use that to recognize the input/edges.

[waclawek.jan]

> Personally I've been using BRR = APBCLK / BAUD for 13+ years, it is simpler to explain/compute.

+1, but the calculation gets more tricky if you want to use the 8x oversampling. OTOH, I'm yet to find a reason for that (except extreme baudrates, which are not a good idea anyway).

JW

[m-electronics]

Hello, I must write here in 2024 also because I´m want to go sure that I understand your calculating right.
You only divide the APBCLK / BAUD_RATE and write this value into the BRR register? Am I right with this?

[waclawek.jan]

Which STM32?

As I've said above, with the default 16-times oversampling, yes.

JW

[m-electronics]

Thanks for your answer 🙂
But I didn´t hear the word "oversampling" before. And I didn´t find something about that until now what it is.
Is it the frequency of the APBCLOCK or what is it?
(I´m new to the topic of programming microcontrollers with the registers only (CMSIS))

[Tesla DeLorean]

The clock frequency of the APB which the particular U(S)ART lives on

APB2 being the fast bus, typically, and where USART1 / USART6 live

[m-electronics]

Ok. So the 16-times oversampling means that the BUS_CLOCK of the BUS where the USART is connected to is16 MHz ?
And 8-times oversampling means that the BUS_CLOCK of the BUS where the USART is connected to is 8 MHz?

And how is the calculation of the BRR value done when the BUS_CLOCK is 8 MHz? I read / heard it is different?

[waclawek.jan]

No.

Oversampling in context of UART means, how many times one bit is sampled. Normally, it's 16x, so the UART's machine has to be clocked at a frequency which is 16x the UART baudrate.

That's what the integer part of the divider ensures; however, the UART clock generator is not integer-divider but fractional-divider (look up either this or "fractional-N divider"). The resulting clock is not entirely regular, but in average it performs quite well even if the APB clock is not integer-divisible by baudrate*16.

The STM32 UART has an optional mode where oversampling is not 16x but 8x, see OVER8 bit.

Read the UART chapter in RM, this is described there.

JW